CPC Z80 buses and synchronous design

[doragasu]

I would like to know if digital interfaces to the Z80 buses inside the CPC can be designed fully synchronous.

Having a look to the Z80 CPU User's Manual it would seem so:



For reads, I can remove data from the bus at the end of T3 (when both #mreq and #rd are removed). For writes, I can easily obtain the data at the end of T2. But I'm asking because some time ago I made a MBC3 memory controller for the Gameboy, and I had to go the asynchronous way because even though the Gameboy CPU is a Z80 derivative, it looks like it has different timigs. E.g. this is the write cycle (extracted from here):



Write signal is not stable at the beginning of neither a rising nor a falling edge, so design cannot be synchronous (unless of course if you decide using another independent and much higher clock and implement a proper clock domain change, that is something I would like to avoid).

So the question is: are the graphs from the Z80 User Manual correct? Can the interface be made in a fully synchronous way?

[gerald]

The user manual is correct.
The traces on the gameboy does not show the actual Z80 clock, but a slower one.
I also have doubt that the others signals straight from the Z80.

[andycadley]

It's worth remembering that the Gameboy CPU isn't a Z80 derivative. It's more like an 8080 derivative, with some of the Z80 instructions borrowed and a few of it's own thrown in for good measure (along with borrowing Z80 assembly syntax, rather than 8080, presumably because it was more well known). I doubt they were too worried about bus compatibility, they removed the entire I/O space so peripherals designed for the Z80 weren't going to be compatible anyway.

[doragasu]

Thanks for the info!

Didn't know the DMG CPU was derived from the 8080, everywhere I read before listed it as a modified Z80.