People,
Here is a schematic and documentation for a conversion of the CPC to enhance the motherboard with more capabilities.
The zip file is a Word 2010 document and details what the intention of the changes mean for an AMSTRAD CPC classic 6128 only. As for an implementation on the CPC464 or 664 or the plus ranges of the CPC, they are not possible right now as I don't have any of them to work on.
Hope people find this information useful.
rpalmer
A 160MHz Cyclone II to add DMA to a 4MHz CPU! :D Why not.
Bryce.
One little thing (you probably already know). There are already some expansions which run well with a 6 MHz Z80, and others don't.
That's an interesting project. I need to study this in greater detail. :)
GUNHED,
Yes I knew of projects pushing the CPC to 6MHz, but they just change the crystal from 16MHz to 24MHz (to get 6MHz) to the CPC.
My project will simply bypass the Gate Array all together to feed the CPU whatever clock it can handle from the FPGA.
rpalmer
Quote from: rpalmer on 21:39, 04 September 19
GUNHED,
Yes I knew of projects pushing the CPC to 6MHz, but they just change the crystal from 16MHz to 24MHz (to get 6MHz) to the CPC.
My project will simply bypass the Gate Array all together to feed the CPU whatever clock it can handle from the FPGA.
rpalmer
But that would loose sync with a lot of the other hardware in the CPC. How would memory access then work, or will this only work when the entire internal RAM is no longer used?
Bryce.
"bypass the Gate Array all together"
You mean that this will be asynchronous with the rest chipset like i.e an Amiga accelerator?
Quote from: Bryce on 07:42, 05 September 19
But that would loose sync with a lot of the other hardware in the CPC. How would memory access then work, or will this only work when the entire internal RAM is no longer used?
Bryce.
The FPGA board auto configures into 2 states.
With just the FPGA and a replacement of the DRAM with a SRAM replacement the board works in unison with the current cpc and only provides the DMA functions.
The other state requires more boards to replace the various chips as the documentation mentions and these all allow the FPGA to do all of the memory access control leaving the gate array to only handle the requested video data it requests and gets via the FPGA.
rpalmer
Quote from: GUNHED on 11:36, 04 September 19One little thing (you probably already know). There are already some expansions which run well with a 6 MHz Z80, and others don't.
That's an interesting project. I need to study this in greater detail. :)
https://www.ebay.com.au/itm/165987135024?hash=item26a59aae30:g:HFkAAOSw5J1fMkZ~
is this one of them? Expensive for 2Mhz though.
The HD64180 suxx badly, it lacks some of the undocumented Z80 instructions.
Furthermore it only uses 19 pins for address decoding (the Z180 uses 20!).
I have developed some initial documentation on the DMA/Accelerator board and I have a rare 20 MHz Z80 CPU (also have the 10 and 8 MHz ones as well).
Also here are the current eagle schematics for the boards.
Will you make a prototype by yourself? Very interesting project btw. :) :) :)
EDIT: imho Option #2 is of greater interest. But wouldn't it be better just do use a new CPC motherboard instead of soldering out all these chips. There are already PCBs being equal to the CPC. Could be more easy to put chips on a new PCB instead of use the regular 6128 pcb. What do you think?
Also a new CPC6128 PCB could be slightly altered compared to the original, for example:
- add 8. bit to printer port (just one track)
- add a 2-4 decoder to support 4 floppy disc drive (great way to copy between 3", 3.5", 5.25" and floppy-emulator)
It would save original CPC6128's from getting broken by accident (desolder chips it not completely easy) and allow us to have everything with a socket from the beginning. :)
This project is very interesting! 20 MHz would be a real gem for quite some applicatons. :) :) :)
the Terasic T-Rex gives an awesome CPC at 24Mhz
https://www.cpcwiki.eu/index.php/CPC_TREX
Just I wonder if those GPIOs could be used for a real expansion port emulation - to plug an Mx4 into it.
Sure, but it's not sold since 2 decades nearly. And it has no Z80!
Back to topic! One of the great advantages of this project here is, that we have a Z80 running at 20 MHz. :)
If you are going to make a Z80 on a board, why not two?
https://archive.org/details/byte-magazine-1978-07
see page 60.
Supporting an SMP system with multiple Z80 cores is still on my wishlist :)
You mean such thing?
The ZedRipper: Part 1 – chrisfenton.com (http://www.chrisfenton.com/the-zedripper-part-1/)
Nice project :)
But I would like to have a real SMP system (all cores have access to the same memory and I/O).
With this ZedRipper you have in fact 15 seperated Z80 computers (and 1 "server") packed in one case.
Quote from: Prodatron on 10:34, 21 September 23Nice project :)
But I would like to have a real SMP system (all cores have access to the same memory and I/O).
With this ZedRipper you have in fact 15 seperated Z80 computers (and 1 "server") packed in one case.
The Project I posted has 2 z80s sharing the same ram accessing it on alternate clock cycles.
Likely this can method can work on cpc too if one accesses cpc hardware but the other just accesses cpc ram perhaps
The Z80 is very bus-heavy, I can't imagine you'd actually gain much by sharing the entire bus between them - it just seems like they'd hinder each other. And there aren't really suitable instructions for atomic synchronization between the two CPUs (unless you provide some mechanism for a CPU to halt the other temporarily).
I think if you wanted a dual Z80 system it'd be better to give each it's own memory and divvy up tasks between them, using IO signals/interrupts to trigger events on the secondary CPU.
Quote from: zhulien on 01:57, 22 September 23Likely this can method can work on cpc too if one accesses cpc hardware but the other just accesses cpc ram perhaps
In the CPC the alternate clock cycles are already taken by the GateArray.
Quote from: eto on 11:30, 23 September 23Quote from: zhulien on 01:57, 22 September 23Likely this can method can work on cpc too if one accesses cpc hardware but the other just accesses cpc ram perhaps
In the CPC the alternate clock cycles are already taken by the GateArray.
if that is the case, can a 2nd Z80 be exactly synced with the GateArray if it only shares (new pageable) memory with the current Z80?
You should replace the RAM with some, which is 4MHz clocked (not 2MHz).
Then you could access it e.g. with 3x Z80 and 1x Gate Array.
@andycadley: Indeed, it will be necessary to have some additional thing, which HALTs the other Z80 if one does a special OUT (can be compared with a "global" DI).
Having this, I can imagine that a pretty cool SMP multitasking/multiprocessing scheduler can be implemented. Dr.Zed was planning such a multicore Z80 system in FPGA since years for a SymbOS system.
Quote from: Prodatron on 18:51, 23 September 23You should replace the RAM with some, which is 4MHz clocked (not 2MHz).
Then you could access it e.g. with 3x Z80 and 1x Gate Array.
@andycadley: Indeed, it will be necessary to have some additional thing, which HALTs the other Z80 if one does a special OUT (can be compared with a "global" DI).
Having this, I can imagine that a pretty cool SMP multitasking/multiprocessing scheduler can be implemented. Dr.Zed was planning such a multicore Z80 system in FPGA since years for a SymbOS system.
I was more-so thinking along lines of
Current CPC hardware+RAM<-->Current Z80<-->Common RAM invisible to GA<-->2nd Z80<-->possibly more banked RAM visible to only 2nd Z80
Quote from: zhulien on 06:00, 20 September 23If you are going to make a Z80 on a board, why not two?
https://archive.org/details/byte-magazine-1978-07
see page 60.
Nice!
At home I have a Genie IIIs with an 8 MHz Z80 and it got a nice (similar to ECB) expansion bus internally. There is the Ultra/8 card added: It contains another Z80 with own 64 KB RAM.
However, both Z80 CPUs can access the same RAM area (can be defined in size and location)
Very nice system, but today I know only one other person working with that power machine too.