Author Topic: Gate array decapped!  (Read 35388 times)

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Offline rpalmer

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Re: Gate array decapped!
« Reply #225 on: 15:57, 14 May 19 »
The current version of the Gate Array Decapped (both the PDF and verilog) will not work with a CPC6128, but could work with the 464/664.

People will ask what make me say this?
Well checking the the Gate Array PDF and subsequent verilog code shows it DOES NOT output the data lines for the PAL chip as seen on the 6128 schematic. The schematic does not show these as being latched, so it must be within the Gate Array and issued by the Gate Array when accessing memory. The verilog ONLY has the data lines defined as "input" which is the main reason why it will not work as expected on a 6128.

Another issue I have seen with the whole breakdown of the GA is that the 4 MHZ and 1 MHz clock signals do not need to be via the "sequencer". It can be generated through 4 flip-flops. I suspect the sequencer should only be for the handling of reading/decoding and displaying video data.
Attached if a reformatted version (less the 31 colors stuff) with comments where the initial issue lies.