r005.8.16c4 : Z80 instruction timing effort, all main instructions timing fixed in MEM_wr:slow mode except one (for me 2A does take 4 NOPs...)
WAIT_n generator updated : for instruction using 5T during M1 cycle, I insert two WAIT_n (experimental)
Tests done :
* Still Rising : no more pixel garbage in plasma using MEM_wr=slow
* 30YMD : main menu (with cursor) running fine using MEM_wr=slow
It's still a candidate version (c4 equals 4th backup of wip). I could only give two days of full work on this realise (c3+c4)... I do also a lot of other activities theses holidays. Have fun !
https://www.youtube.com/watch?v=ovAuDRD2wj4Tests done:
* @00:20 Wunder.bar 2017 OK
* @02:30 Logon's run - 3D meets the aging bits 2017 OK : does not freeze
* @06:30 Still Rising (Vanity) 2013 OK : plasma unlocked
* @12:40 Batman 2015 KO : chip flying ground full of pixel garbage (CRTC offset ?)
* @24:00 Ecole buissonière 2000 OK
* @34:00 30YMD 2016 menu OK, demo GPA KO : a lot of garbage lines (CRTC offset ?), same problem in r005.8.16c3 <= oups, 30YMD's GPA runs better using CRTC0 ^^'