Author Topic: Gate array decapped!  (Read 31464 times)

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Offline arnoldemu

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Re: Gate array decapped!
« Reply #150 on: 22:06, 14 September 16 »
Sure, the EPROM act as a look-up table to set the good software palette.
But... What about directly using the KC Compact hardware palette ? Can you access the 64 colours?
No. You would need to modify the ROM or the PCB to do that.
My games. My Games
My website with coding examples: Unofficial Amstrad WWW Resource

Offline TotO

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Re: Gate array decapped!
« Reply #151 on: 22:18, 14 September 16 »
OK.  8)
"You make one mistake in your life and the internet will never let you live it down" (Keith Goodyer)

Offline TotO

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Re: Gate array decapped!
« Reply #152 on: 22:25, 17 September 16 »
Thanks to gerald for his amazing work... I have started to redo the GA "core" into a CPLD using the schematic method.
The idea is to make working all things that are not related to the display. To confirm his work, I hope to be able to ring the bell!  ;D
« Last Edit: 01:17, 18 September 16 by TotO »
"You make one mistake in your life and the internet will never let you live it down" (Keith Goodyer)

Offline ||C|-|E||

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Re: Gate array decapped!
« Reply #153 on: 22:54, 17 September 16 »
I really have no time for anything until the end of the next week, but I just wanted to pop in an say that this is and amazing collaborative work guys!!  :-* :-*

Offline Executioner

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Re: Gate array decapped!
« Reply #154 on: 10:36, 18 September 16 »
It's rather different from FPGAmstrad which is an adaptation of java emulation with Javacpc or it's finally the same "code" ?

Probably not, JEMU/JavaCPC, like most other emulators, doesn't use GA shift registers and a 16 MHz pixel clock (although it probably should to be totally accurate :) )

Offline DaDMaN

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Re: Gate array decapped!
« Reply #155 on: 23:38, 19 September 16 »
Hi! One guy Ash Evans has coded a 40010 Verilog implementation based on @gerald PDF. I've been talking this afternoon with Ash about this project and this is the results.

Here is the source code:
[VeriLog] // // Amstrad CPC 40010 Gate Array implementation in Verilog. // //

 :D
« Last Edit: 23:43, 19 September 16 by DaDMaN »

Offline dragon

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Re: Gate array decapped!
« Reply #156 on: 23:55, 19 September 16 »
One cuestión is posible create a pre-sic  fpga replacement?. Knowing the other sources as crtc have verilog implementación.

Offline robcfg

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Re: Gate array decapped!
« Reply #157 on: 08:35, 20 September 16 »
It should be possible but you'll have to extract the gates and connections from the picture first (which is a huge job) and then create a vhdl or similar model.

You'd have also the problem of soldering the replacement on the board, as the preAsic has a lot of tiny pins and the replacement chip would be probably bigger.

Offline PulkoMandy

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Re: Gate array decapped!
« Reply #158 on: 10:47, 20 September 16 »
The main problems you will have with an FPGA:
- It is hard to find parts with 5V supply or even 5V-tolerant I/Os. You can't easily use a 3.3V part.
- An FPGA is volatile (like RAM), so it needs something to load code on it. Some FPGAs have a bootstrap system and they can load code from an external serial ROM.


FPGA is not "magic chip that can replace everything".


You will have better chances with fitting the gate array implementation in a CPLD (which is more like EEPROM), if you can find one large enough to fit everything.

Offline dragon

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Re: Gate array decapped!
« Reply #159 on: 11:19, 20 September 16 »
It should be possible but you'll have to extract the gates and connections from the picture first (which is a huge job) and then create a vhdl or similar model.

You'd have also the problem of soldering the replacement on the board, as the preAsic has a lot of tiny pins and the replacement chip would be probably bigger.

I not speaking about made a clone Gate by Gate of the pre-asic. If not made a own alternative  implementación of the  pre-asic  to salve the cpc dead.

Gate array in pre-asic. Have a diferent memory controller to the New ram managent. But the computer not used these  ram from factory uses the older.

So if we have a vhdl of the Gate array and we have a vhdl of the 6845 crtc. And vhdl of pal.  I speaking about only connet the three implementations between It internally  into a cpld/fpga pin compatible or to board adapter compatible.

Arnold 6 or So.


But yeah. Solder It should be a nightmare  :)
« Last Edit: 11:25, 20 September 16 by dragon »

Offline gerald

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Re: Gate array decapped!
« Reply #160 on: 14:10, 20 September 16 »
The main problems you will have with an FPGA:
- It is hard to find parts with 5V supply or even 5V-tolerant I/Os. You can't easily use a 3.3V part.
- An FPGA is volatile (like RAM), so it needs something to load code on it. Some FPGAs have a bootstrap system and they can load code from an external serial ROM.


FPGA is not "magic chip that can replace everything".


You will have better chances with fitting the gate array implementation in a CPLD (which is more like EEPROM), if you can find one large enough to fit everything.
You will also have hard time tring to solder your replacement FPGA board to the 100 fine pitch footprint on the PCB. Not impossible, but a lot of trouble ahead.

Regarding CPLD,  you will have to go for the biggest. The GA does not fit a XC95144XL as it require 166DFF/Latch + glue.
It would fit the XC95288XL which is the large CPLD xilinx offer with 5V tolerant IO.

BTW, CPLD (at least xilinx ones) also need to be initialized at power up, but the configuration is stored internally and init done automatically. Bigger is the PLD, longer is the init phase.

Offline Bryce

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Re: Gate array decapped!
« Reply #161 on: 15:25, 20 September 16 »
So you'd have to modify the CPCs reset circuitry to allow for the long init time?

Regarding the soldering. It might be easiest to solder a 100pin PLCC socket to the PCB and then make a PLD solution that can plug into this?

Bryce.

Offline gerald

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Re: Gate array decapped!
« Reply #162 on: 19:50, 20 September 16 »
So you'd have to modify the CPCs reset circuitry to allow for the long init time?
May be. On early 464, the reset is short enough to prevent sampling of IO on rising edge of reset signal in my ram/flash:CF extension.
That is, the reset is released before the PLD is configured.
That's not happing on later CPC models.
That's how I discovered that init time.

Regarding the soldering. It might be easiest to solder a 100pin PLCC socket to the PCB and then make a PLD solution that can plug into this?
The pre-asic package is quite exotic to today standard. I doubt it's easy to find a socket, and custom ones cost an arm.

Offline freemac

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Re: Gate array decapped!
« Reply #163 on: 22:39, 20 September 16 »
Probably not, JEMU/JavaCPC, like most other emulators, doesn't use GA shift registers and a 16 MHz pixel clock (although it probably should to be totally accurate :) )
It's the same. FPGA is a reprogrammable CPLD. GateArray is a CPLD.
I'm currently experimenting some vhdl testbench extract from JavaCPC in order to compare vhdl (or verilog) gatearray each other.

Ok, let's catch them all : FPGA-GA - CPCWiki (entry list)  ;)

If you succeed extracting original GateArray vhdl/verilog, you can poke me :)

Extracting CRTC1 shall interest me (CRTC0 also, but it is really too hard to implement in small FPGA yet)
« Last Edit: 23:07, 20 September 16 by freemac »

Offline freemac

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Re: Gate array decapped!
« Reply #164 on: 22:44, 20 September 16 »
The main problems you will have with an FPGA:
- It is hard to find parts with 5V supply or even 5V-tolerant I/Os. You can't easily use a 3.3V part.
- An FPGA is volatile (like RAM), so it needs something to load code on it. Some FPGAs have a bootstrap system and they can load code from an external serial ROM.


FPGA is not "magic chip that can replace everything".


You will have better chances with fitting the gate array implementation in a CPLD (which is more like EEPROM), if you can find one large enough to fit everything.
Old components are 5V but they speaks each others at 3.3V in fact :D

FPGAmstrad - CPCWiki Test of a real Zilog 80
« Last Edit: 22:50, 20 September 16 by freemac »

Offline Bryce

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Re: Gate array decapped!
« Reply #165 on: 10:26, 21 September 16 »
The pre-asic package is quite exotic to today standard. I doubt it's easy to find a socket, and custom ones cost an arm.

Oh yeah, I forgot that. It's one of those rectangular ones isn't it? Not square. Pain in the arse.

Bryce.

Offline dragon

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Re: Gate array decapped!
« Reply #166 on: 14:10, 21 September 16 »
« Last Edit: 14:45, 21 September 16 by dragon »

Offline robcfg

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Re: Gate array decapped!
« Reply #167 on: 12:41, 18 October 16 »
More awesome news from decapping land!


Here you have the metal layer pictures of 40007 gate array, 40008 gate array and the infamous ACID chip.

Offline Gryzor

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Re: Gate array decapped!
« Reply #168 on: 12:48, 18 October 16 »
Ok, question: who's got a source to make poster prints out of these beauties?

Offline robcfg

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Re: Gate array decapped!
« Reply #169 on: 12:50, 18 October 16 »
Indeed, they look beautiful.


My favourites are the 40010 and 40008, hehe  :D

Offline Bryce

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Re: Gate array decapped!
« Reply #170 on: 13:14, 18 October 16 »
Ok, question: who's got a source to make poster prints out of these beauties?

I have a source that can even print these onto banner cloth, so you can hang it as curtains :D

Bryce.

Offline Gryzor

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Re: Gate array decapped!
« Reply #171 on: 13:18, 18 October 16 »
Eh... I don't think she'd go for it :D

Offline dragon

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Re: Gate array decapped!
« Reply #172 on: 13:24, 18 October 16 »
Ok, question: who's got a source to make poster prints out of these beauties?


You can make a parasol(i unkown the english word) for car, then all pople can view it :)


Downloading...

Offline Gryzor

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Re: Gate array decapped!
« Reply #173 on: 13:32, 18 October 16 »
Ah you mean for the windshield, right? That's an idea! :D

Offline Bryce

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Re: Gate array decapped!
« Reply #174 on: 13:40, 18 October 16 »
I think he means a complete car cover: http://www.5starshine.com/images/coverking/carcoverbigenzo.jpg

Bryce.