Author Topic: Gate array decapped!  (Read 31440 times)

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Offline robcfg

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Re: Gate array decapped!
« Reply #175 on: 13:51, 18 October 16 »
Nope, but would be awesome indeed!  ;D


He refers to a windshield shade.

Offline dragon

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Re: Gate array decapped!
« Reply #176 on: 13:57, 18 October 16 »
Yeah some like these lateral, or frontal, or in the back:

Is very easy find sites do it :

http://www.getsingular.com/parasoles-coche-personalizados.html

[youtube]https://www.youtube.com/watch?v=0VzB_LmGdO4[/youtube]

Offline dragon

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Re: Gate array decapped!
« Reply #177 on: 14:05, 18 October 16 »
So the 40010-A is the misterius reserved to the finish right? :).

Online Bryce

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Re: Gate array decapped!
« Reply #178 on: 14:08, 18 October 16 »
Yeah, but get the Plus ASIC version printed, it has more colours :)

Bryce.

Offline dragon

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Re: Gate array decapped!
« Reply #179 on: 14:26, 18 October 16 »
One chip per window, the acid in front then you are more protected.

First open 40908 suprise surprise is a thosiba ic. Other gate array new to the family. time to investigate thosiba ics .Maybe the asic manufactuirer is thosiba.

In the 40007 my theory is correct is the ferranti ula 5000R series. If you take in the zx spectrum book the figure 5-24 :R series matrix cells (page  60).

The cells in the ic are exactly equal :)

The 40008 as my theory (yepahhh!!). Is another ferrenti ic chip from 5000r(same model ic?) or maybe 6000r series ula.

Pages 59-70 in zx spectrum book covers 40007 and 4008 strtucture :)
« Last Edit: 14:40, 18 October 16 by dragon »

Offline robcfg

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Re: Gate array decapped!
« Reply #180 on: 14:34, 18 October 16 »
So the 40010-A is the misterius reserved to the finish right? :) .


I have good news for you8)

Offline dragon

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Re: Gate array decapped!
« Reply #181 on: 14:54, 18 October 16 »
You can count the files x cell please , my pentium 4 is so slow with the picture is more bigger that the other?.

Offline robcfg

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Re: Gate array decapped!
« Reply #182 on: 15:53, 18 October 16 »
I'm astonished!


40010-36AA has 18 rows and 74 coumns (37 pairs), while 40010-37AA has 21 rows and 82 columns (41 pairs)...


Now, I don't know if @gerald will have the time (or the will) to check them for differences.


Another Amstrad fact learnt today  :D

Online Bryce

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Re: Gate array decapped!
« Reply #183 on: 17:11, 18 October 16 »
I'm astonished!


40010-36AA has 18 rows and 74 coumns (37 pairs), while 40010-37AA has 21 rows and 82 columns (41 pairs)...


Now, I don't know if @gerald will have the time (or the will) to check them for differences.


Another Amstrad fact learnt today  :D

That doesn't necessarily mean that they function differently, it may just be a different die with the same mask.

Bryce.

Offline dragon

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Re: Gate array decapped!
« Reply #184 on: 17:23, 18 October 16 »
That doesn't necessarily mean that they function differently, it may just be a different die with the same mask.

Bryce.

But my theory was right. :) . And now the name in schematics pins compatibility have sense. And is a mystery anyway :)

The model should be in the gate array pdf i put time ago.

The other mistery is the 40007-40008, i think is the same ula. So amstrad made changes to the circuit  to eliminate the heat.

About the acid thosiba makes sense remember the joint  history of thosiba-lsi

Online Bryce

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Re: Gate array decapped!
« Reply #185 on: 17:32, 18 October 16 »
Hot spots can occur if lots of fast switching transistors are physically close to each other on the die. To reduce this you spread them around the die by shifting functions from one area to another, but this can force you to re-assign the I/O pins. This can still even happen with modern CPLDs/FPGAs and it's a pain in the arse when you need to do it late in a program. Something like this was probably the reason for the pinout changes.

Bryce.

Offline 1024MAK

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Re: Gate array decapped!
« Reply #186 on: 18:12, 18 October 16 »
One problem with some ULA chips is that the gate propagation delay changes significantly as the chip temperature increases. This affects the higher speed sections of a design.

That's the problem that Acorn had with the ULA used as the Videoproc in the BBC Micro (hence why a heatsink was fitted to early ULA chips).

In the ZX Spectrum, the vertical lines on the display when inverting, or flashing the character cells is also a propagation delay issue.

Most ULA chips from Ferranti have logic that operates at a lower voltage than the supply. So the chip includes many series regulators around the outside of the logic area. These produce a fair bit of the heat in the chip.

Mark
« Last Edit: 18:19, 18 October 16 by 1024MAK »
Looking forward to summer in Somerset :-)

Offline gerald

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Re: Gate array decapped!
« Reply #187 on: 19:12, 18 October 16 »
That doesn't necessarily mean that they function differently, it may just be a different die with the same mask.

Bryce.
My bet is just a trade-off between time to market and cost.
37AA version (biggest) done as fast as possible.
36AA version (smallest) is just a re-layout of the same logic on a smaller array to reduce cost once the functionality has been validated.
A quick look show that the overall floor-plan is identical (even the layout of the top-left corner).
The 37AA has far more un-used cells. My bet is that the netlist are identical, but I am not sure I will check it ;)

I may give a shot at 40007/40008 just to understand what has been fixed between the 2 version. The GA used is the same for both (and confirm the 40007/40008 are footprint compatible)

Offline dragon

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Re: Gate array decapped!
« Reply #188 on: 20:04, 18 October 16 »
Only say the count made by robcfg  21X82=1722 In the pdf=LL3170  Match perfect with the hsg3170 changing the initials to sgs nomenclature.

And of course the other ic count 18x74=1332 in the pdf=LL3130 Hsg3130 with sgs nomenclature.

 :)


Offline ||C|-|E||

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Re: Gate array decapped!
« Reply #189 on: 22:08, 18 October 16 »
Aaah... Toshiba, the same brand that made my TV is also the one behind the evil ACID?  :-X

Offline dragon

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Re: Gate array decapped!
« Reply #190 on: 00:35, 20 October 16 »
My bet is just a trade-off between time to market and cost.
37AA version (biggest) done as fast as possible.
36AA version (smallest) is just a re-layout of the same logic on a smaller array to reduce cost once the functionality has been validated.
A quick look show that the overall floor-plan is identical (even the layout of the top-left corner).
The 37AA has far more un-used cells. My bet is that the netlist are identical, but I am not sure I will check it ;)

I may give a shot at 40007/40008 just to understand what has been fixed between the 2 version. The GA used is the same for both (and confirm the 40007/40008 are footprint compatible)


About year 95 Roland Perry tell this in amstrad group.


"I happen to know that the first chips were Ferranti ULAs made exactly to Amstrad's design, while later models were SGS custom chips which were plug compatible, but not identical at the gate level, allegedly."




I not know what chips they  speak in the part of diferent at gate level.


40008/10 or aa37 aa 36

« Last Edit: 16:08, 25 October 16 by Gryzor »

Offline RichTW

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Re: Gate array decapped!
« Reply #191 on: 13:10, 23 November 16 »
Hi all!


I just joined up because I've always been fascinated by the unusual video specifications of the CPC and wanted to congratulate all involved in putting together the schematics for the gate array!


I'd always wondered how the hardware palette colour order came to be - I could never determine the logic behind it (even though there appeared to be some order), and was curious about why those particular duplicate colours dropped out of the logic.  So with these schematics, finally it's possible to see exactly how it works, and it's as fascinating and yet as obscure as I might have hoped!  :)   The tristate logic was definitely an unusual feature.


I think I've spotted a small error in the schematic: in the Colour number to RGB decoder, gate U1806 is inverting the wrong input: it should be inverting COLOUR2, not COLOUR0 - this then produces the same results as the hardware colour numbers.


Out of interest, why is there the popular view that originally a 64 colour palette was intended?  Seems to me this would require a really different design - tristate logic would no longer be an option, for a start.  The 27 colour palette seems like a hack which comes from exploiting the tristate outputs without requiring a lot of extra logic to achieve it, compared to a binary (on or off, 8 colour) palette.

Online TotO

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Re: Gate array decapped!
« Reply #192 on: 14:15, 23 November 16 »
Out of interest, why is there the popular view that originally a 64 colour palette was intended?  Seems to me this would require a really different design - tristate logic would no longer be an option, for a start.  The 27 colour palette seems like a hack which comes from exploiting the tristate outputs without requiring a lot of extra logic to achieve it, compared to a binary (on or off, 8 colour) palette.
As you said, it look to be a hack to exploit the tristate outputs.
With that, the GA require 3 less pin to display the coulours and the bit5 of the colour register was left unused.
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Offline arnoldemu

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Re: Gate array decapped!
« Reply #193 on: 15:00, 23 November 16 »
Out of interest, why is there the popular view that originally a 64 colour palette was intended? 
There is space in the register for 2 bits for each of r,g and b making 64 colours.

I think that is the only reason this view is held.



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Offline gerald

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Re: Gate array decapped!
« Reply #194 on: 18:31, 23 November 16 »
I think I've spotted a small error in the schematic: in the Colour number to RGB decoder, gate U1806 is inverting the wrong input: it should be inverting COLOUR2, not COLOUR0 - this then produces the same results as the hardware colour numbers.
Well spotted !
That's a miss in the 'simplification' process.
Updated version attached. There is also a fix in the color decode mux (label where missing on output bus).

Offline PulkoMandy

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Re: Gate array decapped!
« Reply #195 on: 11:57, 24 November 16 »
that 64 colour theory is somewhat coming from my own speculations. What I *think* could have happened is:
- The registers for the gate array were initially designed with 64 colors in mind (2 bit of each red, green, blue) - there is still space for it in the register map, with 1 bit being unused.
- This would have required 6 output pins from the gate array to generate the video signal
- People kept adding features to the chip, and at some point it did use all the 40 pins of the largest package they could get
- They had to free some more pins for other features, and at some point had to settle for video output on just 3 pins
- Fortunately, by using the high impedance trick, this results in 27 colors, instead of just 8, making it a not so bad tradeoff

Of course, I can be wrong and the 27 colors tricks may have been planned from the start. We would have to check with the people who designed the hardware to be sure.

Offline andycadley

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Re: Gate array decapped!
« Reply #196 on: 23:56, 24 November 16 »
The way I always heard it back in the day is that the original design called for 16 colours, then the designers got clever and spotted the tristate hack could be done pretty much for free and so extended the register design to allow it to work.

Offline RichTW

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Re: Gate array decapped!
« Reply #197 on: 00:01, 25 November 16 »
That sounds feasible.  I can imagine they might've been going for an RGBI type palette, like the Spectrum, and realised that if they had to have tristate outputs, they may as well find a way to control each one individually instead of all-full or all-half.

Offline 1024MAK

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Re: Gate array decapped!
« Reply #198 on: 14:24, 25 November 16 »
I suspect that the hardware designers took inspiration from the other existing home micros. You had the ZX Spectrum with 15 colours (7 full intensity "bright" colours, 7 "normal" intensity colours plus black), the BBC model B had 8 colours, the C64 had 16 colours, so the minimum that the CPC should have was 16 colours. But going up to 64 colours may have increased the cost too much (remember the market it was aimed at).

But could they do any better? Well, Sinclair, with their design of ZX81 ULA video circuity had already demonstrated that digital logic could output three voltages instead of just two digital logic levels (low = sync, medium = black signal, high = white level). So presumably someone had a light bulb moment!

The result is the 27 colour system  :D

Mark
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Offline dragon

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Re: Gate array decapped!
« Reply #199 on: 15:20, 25 November 16 »
At the time of cpc release, the majority of enginners was graduate recentlly. Mej electronics was found litte time early.

Its nornal the take a look a other systems as reference.

Anyway at the finish of the day these years. The final especification was conditioned to the space in the ula/cost.

Really, i think if in these days. Amstrad go first with sgs instead of ferranti. We can have a totally diferent especification in the gate array. Sgs apperars have more gates  at same cost.