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General Category => Amstrad CPC hardware => Topic started by: robcfg on 18:54, 12 April 16

Title: Gate array decapped!
Post by: robcfg on 18:54, 12 April 16
Hello everyone!


As I told in another thread, @Cpcmaniaco (http://www.cpcwiki.eu/forum/index.php?action=profile;u=23) and I sent 4 different Gate Array chips (40007, 40010, PreASIC and ASIC) to Sean Riddle (Sean Riddle's Home Page (http://www.seanriddle.com)) for decapping.


Today he sent me the first picture, which is the 40010 GA. I have to say it looks impressive, and finally we can have a peek at the inner working of the GA.


I uploaded the picture to the Gate Array wiki page (http://cpcwiki.eu/index.php/Gate_Array#Pictures).


Enjoy!
Title: Re: Gate array decapped!
Post by: Singaja on 19:06, 12 April 16
Could this be done with ASIC?
Title: Re: Gate array decapped!
Post by: dragon on 19:19, 12 April 16
My 3mb adsl is colapsed to view the foto. good work guys!!.
Title: Re: Gate array decapped!
Post by: robcfg on 19:19, 12 April 16
I guess so, that's why we sent him a PreASIC and an ASIC chip.
Title: Re: Gate array decapped!
Post by: dragon on 19:22, 12 April 16
Me da error la foto a pantalla completa os pasa a vosotros dice no se puede mostrar la imagen porque contiene errores.

Vale arreglado, la he descargado con el jdowloader jeje.
Title: Re: Gate array decapped!
Post by: Gryzor on 19:33, 12 April 16
It was probably a downloading error, the image is perfect - if it wasn't jDownloader wouldn't help :)


Amazing artwork for a wall print. I'm thinking this, an armchair, drugs. Duuuuude!
Title: Re: Gate array decapped!
Post by: gerald on 19:35, 12 April 16
I uploaded the picture to the Gate Array wiki page (http://cpcwiki.eu/index.php/Gate_Array#Pictures).
Is that the highest resolution available ? Some features are difficult to see.
Title: Re: Gate array decapped!
Post by: Arnaud on 19:42, 12 April 16
What can we do with it ? Improve emulation / FPGA ?
Title: Re: Gate array decapped!
Post by: gerald on 19:54, 12 April 16
What can we do with it ? Improve emulation / FPGA ?
Yes. But I do not think there is much to be found on the 40010/40007
However, the ASIC picture would really help improving emulation, be it HW or SW.
Title: Re: Gate array decapped!
Post by: dragon on 20:01, 12 April 16
Yes. But I do not think there is much to be found on the 40010/40007
However, the ASIC picture would really help improving emulation, be it HW or SW.

Diferent tecnology, if at the finish the 40007 is the ferranti 5000 documented in the book of zx spectrum.

Anyway i think it can be good specially to make new pre-asic chips to dead boards, and in the plus range, we can discover why the bugs of plus range.
Title: Re: Gate array decapped!
Post by: Gryzor on 20:15, 12 April 16
Is that the highest resolution available ? Some features are difficult to see.


Might be due to jpeg compression? @robcfg (http://www.cpcwiki.eu/forum/index.php?action=profile;u=4) was kind enough to send me a 160MB version (though in GiMP format, no idea how this compares to TIFF etc), if anyone needs it I'll arrange something :)
Title: Re: Gate array decapped!
Post by: gerald on 20:37, 12 April 16

Might be due to jpeg compression? @robcfg (http://www.cpcwiki.eu/forum/index.php?action=profile;u=4) was kind enough to send me a 160MB version (though in GiMP format, no idea how this compares to TIFF etc), if anyone needs it I'll arrange something :)
160MB is roughly the size of the image linked save in xcf (Gimp). So I guess this is the same resolution.
Title: Re: Gate array decapped!
Post by: robcfg on 20:52, 12 April 16
Same resolution but without compression artifacts.
Title: Re: Gate array decapped!
Post by: dragon on 20:57, 12 April 16
Is a channeled gate array?, So the cells are the in the rows and the space are the interconnecion between cells?.

Channeled Gate Array (https://inst.eecs.berkeley.edu/~ee244/fa97/Lectures/ee2441_1/sld030.htm)
Title: Re: Gate array decapped!
Post by: TotO on 21:07, 12 April 16
If I understand well, it is incredible to know that 40010 GA was designed in 1983 by LSI LOGIC and produced by SGS (ST Microelectronics).
Title: Re: Gate array decapped!
Post by: gerald on 21:20, 12 April 16
Same resolution but without compression artifacts.
Interrested  ;)
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 21:56, 12 April 16
This is amazing! If we had all the data for the ASIC it should be possible to do a perfect FPGA core and a perfect emulator...  :o
Title: Re: Gate array decapped!
Post by: robcfg on 22:39, 12 April 16
Some more info on the picture:


Quote
That pic was composited from 156 pics taken using a 10x objective, and I scaled it down by about 1/2. I also took pics with a 20x objective, but there are 600 of those, so I need a faster way to composite them.


That's some serious amount of work!


Also:


Quote
I was able to figure out the pad numbering from that doc:
Code: [Select]
   5    36 
 6        35




14        26
  15    25


The doc he's referring to is http://matthieu.benoit.free.fr/pdf/amstrad_videogate-array.pdf (http://matthieu.benoit.free.fr/pdf/amstrad_videogate-array.pdf)


@gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) , I sent you a PM  ;)


I'm eager to see the rest of the chips, hehe!
Title: Re: Gate array decapped!
Post by: robcfg on 22:47, 12 April 16
Is a channeled gate array?, So the cells are the in the rows and the space are the interconnecion between cells?.

Channeled Gate Array (https://inst.eecs.berkeley.edu/~ee244/fa97/Lectures/ee2441_1/sld030.htm)


I cannot tell you for sure, as I'm no expert in the field. It looks like one, but I can be wrong.
Title: Re: Gate array decapped!
Post by: Bryce on 22:57, 12 April 16
Very nice work. He obviously knows what he's doing to have freed the metal layer that nicely without damaging it at all. In high-res this should be "decypherable". Massive amount of work though.

Bryce.
Title: Re: Gate array decapped!
Post by: dragon on 23:07, 12 April 16
And what happend with the 40008? i view is selling now alone in ebay. We can make a collect or something. To.have all chips decaped.

Quote

I cannot tell you for sure, as I'm no expert in the field. It looks like one, but I can be wrong.

I 'm not an expert  only supposed, if is this type one of the horizontal metal layers are vccc an the other ground.
Title: Re: Gate array decapped!
Post by: robcfg on 23:13, 12 April 16
Very nice work. He obviously knows what he's doing to have freed the metal layer that nicely without damaging it at all. In high-res this should be "decypherable". Massive amount of work though.

Bryce.


Indeed, but at least, we have a starting point, which is more than we had. Any suggestions on how should we start identifying anything on the image?


Quote
And what happend with the 40008? i view is selling now alone in ebay. We can make a collect or something. To.have all chips decaped.


Well, CPCManiaco spent quite some time digging through all the CPCs he has at hand, but he couldn't find a 40008.


Anyway, I expect the most changes to happen between 40007 and the other two, as 40008 and 40010 have the same pinout.


Of course, it would be nice to have them all decapped  ;)
Title: Re: Gate array decapped!
Post by: dragon on 23:16, 12 April 16
Yeah i suppose it we can buy one thats all :)

And no cpc sacrificed :)

Amstrad 40008 | eBay (http://m.ebay.es/itm/Amstrad-40008-/252343051537?nav=SEARCH)

Yeah the 40007 probably share picture infrastructure with ula spectrum, i think the 40008 is made by lsi (without sgs).

I count 37 cells (it appeared agruped by two in two) *18 rows=666 jaja. counting it alone makes 74*18=1332 cells.

Title: Re: Gate array decapped!
Post by: Gryzor on 09:28, 13 April 16
Crowdfunding? :D


No idea about the industry, but isn't there any software that can help you decipher the whole thing?
Title: Re: Gate array decapped!
Post by: Octoate on 09:50, 13 April 16
No idea about the industry, but isn't there any software that can help you decipher the whole thing?
You can use Degate (Reverse engineering integrated circuits with degate - Home (http://www.degate.org)). Btw, a nice tutorial on how to reverse engineer ICs can be found here (http://siliconzoo.org/tutorial.html).
Title: Re: Gate array decapped!
Post by: TotO on 10:55, 13 April 16
Crowdfunding? :D
Those seven 40008 IC are on ebay months after months and nobody buy them for this price...
I suggest to contact the seller and ask him a more afortable price with shipping to the decapper address.
Title: Re: Gate array decapped!
Post by: Munchausen on 10:58, 13 April 16
You can use Degate (Reverse engineering integrated circuits with degate - Home (http://www.degate.org)). Btw, a nice tutorial on how to reverse engineer ICs can be found here (http://siliconzoo.org/tutorial.html).

Cool software!

Is this image high resolution enough? The screenshots on the Degate page look like they show more detail.
Title: Re: Gate array decapped!
Post by: arnoldemu on 11:09, 13 April 16
I have some 40010 and 40007 here that I was going to send to visual6502 for decapping but never did.
I will check if I have a 40008 (unlikely, but I will check).

Title: Re: Gate array decapped!
Post by: dragon on 11:36, 13 April 16
You can use Degate (Reverse engineering integrated circuits with degate - Home (http://www.degate.org)). Btw, a nice tutorial on how to reverse engineer ICs can be found here (http://siliconzoo.org/tutorial.html).

I read the tutorial, i understand the logic behind it +-, but i no view how applied it to this gate array.

The horizontal metal layers are vcc and ground(is vcc the up or the down?). A connected vcc or ground can be easly view because the horizontal metal layers in each vertical line have intermediate vertical lines (comparing the free  cells in the left upper corner, with full). But i dont understand the vertical pads  crossing the cell , because they have wires connected. I spected the wires be connect to.the red substrate, and vertical pads are the red in the tutorial,
If i supposed the 6 vertical barsin  one cell of the gate array. Are the red in the tutorial ,I little lost :-)

Is the down wire vcc and upper ground?
Title: Re: Gate array decapped!
Post by: robcfg on 11:47, 13 April 16
Good morning!


I just received the picture of the 40226 PreASIC metal layer, you'll find it along the 40010 pictures in the Gate Array (http://cpcwiki.eu/index.php/Gate_Array#Pictures) page.


Sean tells me that he removed the passivation layer and the top metal layer from both chips and will be taking a new set of pictures shortly.


Unfortunately the 40007 broke because of thermal stress, so we'll have to get another one.


Have a nice day!
Title: Re: Gate array decapped!
Post by: TotO on 12:05, 13 April 16
Quote from: robcfg
Unfortunately the 40007 broke because of thermal stress, so we'll have to get another one.
I have some 40007 in stock. I can ship him one of them.

Title: Re: Gate array decapped!
Post by: Cpcmaniaco on 12:10, 13 April 16
Now. I get 1 40008 from ebay, for this experiment.
Title: Re: Gate array decapped!
Post by: Cpcmaniaco on 12:14, 13 April 16
@TotO (http://www.cpcwiki.eu/forum/index.php?action=profile;u=290)   I will bay you 2 40007, 1 for the experiment and 1 for me to replace the other.
Title: Re: Gate array decapped!
Post by: TotO on 12:35, 13 April 16
I have expected that you will require a replacement part too.  ;)
I will provide you free parts and ship them this afternoon!  8)
Title: Re: Gate array decapped!
Post by: dragon on 13:01, 13 April 16
Pre asic =lsi compact gate array. Sea of gates. It appear amstrad have pass in this life with all stages of new technology in gate arrays. It have reference books published.

Thats remember me. Also the acid is reverse enginered. What about sending one to complete the album of pictures of custom ic?

Hi found this curse, i think it can help to undersantd how works the logic of the 40010
https://www.google.es/url?sa=t&source=web&rct=j&url=http://www.csit-sun.pub.ro/courses/vlsi/VLSI_Darmstad/www.microelectronic.e-technik.tu-darmstadt.de/lectures/winter/vlsi/vorlesung_pdf/chap13.pdf&ved=0ahUKEwimjNbxy4vMAhVG1hQKHaHFD2sQFgg4MAk&usg=AFQjCNFARYhNwBskHOmvbPyYVAah9qc9WA&sig2=Gm_oFlQcbWiW22ptFgRHIw (https://www.google.es/url?sa=t&source=web&rct=j&url=http://www.csit-sun.pub.ro/courses/vlsi/VLSI_Darmstad/www.microelectronic.e-technik.tu-darmstadt.de/lectures/winter/vlsi/vorlesung_pdf/chap13.pdf&ved=0ahUKEwimjNbxy4vMAhVG1hQKHaHFD2sQFgg4MAk&usg=AFQjCNFARYhNwBskHOmvbPyYVAah9qc9WA&sig2=Gm_oFlQcbWiW22ptFgRHIw)
Title: Re: Gate array decapped!
Post by: TotO on 15:08, 13 April 16
@TotO (http://www.cpcwiki.eu/forum/index.php?action=profile;u=290)   I will bay you 2 40007, 1 for the experiment and 1 for me to replace the other.
Just sent!  ;)
Title: Re: Gate array decapped!
Post by: gerald on 19:25, 13 April 16
Pre asic =lsi compact gate array. Sea of gates. It appear amstrad have pass in this life with all stages of new technology in gate arrays. It have reference books published.

Thats remember me. Also the acid is reverse enginered. What about sending one to complete the album of pictures of custom ic?

Hi found this curse, i think it can help to undersantd how works the logic of the 40010
https://www.google.es/url?sa=t&source=web&rct=j&url=http://www.csit-sun.pub.ro/courses/vlsi/VLSI_Darmstad/www.microelectronic.e-technik.tu-darmstadt.de/lectures/winter/vlsi/vorlesung_pdf/chap13.pdf&ved=0ahUKEwimjNbxy4vMAhVG1hQKHaHFD2sQFgg4MAk&usg=AFQjCNFARYhNwBskHOmvbPyYVAah9qc9WA&sig2=Gm_oFlQcbWiW22ptFgRHIw (https://www.google.es/url?sa=t&source=web&rct=j&url=http://www.csit-sun.pub.ro/courses/vlsi/VLSI_Darmstad/www.microelectronic.e-technik.tu-darmstadt.de/lectures/winter/vlsi/vorlesung_pdf/chap13.pdf&ved=0ahUKEwimjNbxy4vMAhVG1hQKHaHFD2sQFgg4MAk&usg=AFQjCNFARYhNwBskHOmvbPyYVAah9qc9WA&sig2=Gm_oFlQcbWiW22ptFgRHIw)
Gate array was usually cheaper than an ASIC if you could get your logic in it. I would not be surprised that the plus Asic is also a gate array.
Title: Re: Gate array decapped!
Post by: arnoldemu on 21:16, 13 April 16
I have some 40010 and 40007 here that I was going to send to visual6502 for decapping but never did.
I will check if I have a 40008 (unlikely, but I will check).
I don't have a 40008.

If the 40007 that is being sent also fails to be decapped then I have another we can send and try.
Title: Re: Gate array decapped!
Post by: dragon on 21:24, 13 April 16
And probably made by sgs logic corporation :) .


Investigating I found a a free book about the history of lsi coporation.Curiosity the company begin in 1980.First copy(licensed) the standar Robert Lipp cell design in the 80 for cmos gate array, and later around 1982, they made a joint with thosiba  to desning an asic. They made a vdsli aplication using diferenten licenses.

The question is around 1983 (The c year in the gate array die). They finish with thosiba the LL5000 series gate array. Searching their datasheet  in LL5000 series, it said sgs is a second source with other company.

I autothinking if you are a second source company. And you want your product not have the original code of original manfacturer.But its a second source. Then you use the original number name, but your changue first original name.

So i search  lsi logic corp LL3000 array.

And i found a datasheet of a lsi LL3000 series. And it have and interesting table wihth all submodels.

And two of the submodel in the table are "misteriusly" LL3130 and LL3170 Remember the name of 40008 and 40010 in the service manuals? HSG3130 and HSG3170

As the datasheet says is a "H-CMOS Silicon Gate-Logic array"  HGS=abreviature of H-cmos Silicon Gate logic array ? :)

LL3250 ... - Datasheet Search Engine Download (http://www.datasheetarchive.com/dl/Scans-053/DSAIH00065990.pdf)


 Pd: We need this book:


Databook and design manual : HCMOS macrocells, macrofunctions (Book, 1986) (http://www.worldcat.org/title/databook-and-design-manual-hcmos-macrocells-macrofunctions/oclc/22886464&referer=brief_results)
Title: Re: Gate array decapped!
Post by: pelrun on 07:53, 14 April 16
Looking at the patents a bunch of them have a diagram and description of the basic P/N transistor cell that you can see repeated in our GA. This one has it as Fig. 1:



http://www.google.com/patents/US5079614 (http://www.google.com/patents/US5079614)


One square each of P and N doped diffusion, overlaid by two strips of polysilicon to form transistors, and crossed by VDD and VSS power lines. On our GA there are only minor differences; the second cell has a crossover between the two wells, and the power lines are in the metal layer on top.
Title: Re: Gate array decapped!
Post by: dragon on 15:54, 15 April 16
The big problem as people say earlier, is its lack resolution, i can't watch really where are connected the cables :s.

Maybe is best make an alternative approach.

Take the base cell, and drawn in a paper the basic logicall cells, and,or,nand,nor, etc. Theoricall connected with the base cells.

And then try find these  "figures" in the picture. Then at least is posible find the basic gates, search the wires between cells is more easy. To form macrofunctions
Title: Re: Gate array decapped!
Post by: Gryzor on 16:08, 15 April 16
Can you circle, on the photo, where the problem lies? I'll see if it's on the original image...
Title: Re: Gate array decapped!
Post by: pelrun on 16:21, 15 April 16
I disagree about the resolution; I don't have any problem seeing where the metal traces are joined to the silicon layers, either in the large bus bars or in the finer interconnects. There's very rarely a join in the middle of a track, anyway (they branch off into a stub if there's room) - and even those are distinguishable.


Edit: only talking about the original GA here; the Pre-ASIC is much denser.
Title: Re: Gate array decapped!
Post by: dragon on 19:13, 15 April 16
Quote
author=Gryzor link=topic=11888.msg124813#msg124813 date=1460725733]
Can you circle, on the photo, where the problem lies? I'll see if it's on the original image...

Oh i think its not necessary, i can't simply interpret the pass from theory to the picture.


I disagree about the resolution; I don't have any problem seeing where the metal traces are joined to the silicon layers, either in the large bus bars or in the finer interconnects. There's very rarely a join in the middle of a track, anyway (they branch off into a stub if there's room) - and even those are distinguishable.


Edit: only talking about the original GA here; the Pre-ASIC is much denser.

If you can make an example with one of the cells of the picture. And a equivalence with the therory in paper. I (and others i suppuse :) be grateful, for example who do you distinghs where are connectwd vcc with the vertical lines in the power metal bars.

Why the vertical bar  in the middle are less fat that the other?

Where is connected the wires to the metal bars or transistors when they are in the bars
 In the theory the vertical bars have  connections in the two sides around the power bars, but it have in these gate array?. I don't have view a wire connected  in the upper part of vcc vertical bar.

I mean i understand the theory in paper. But i can't interpret how is connected the cells, because i can't view the transistors where they are connected to compare the cell structure with the paper theory structure.

I'm sure bryce,gerald and you and other people  not have problems to figure how is connected, but i non an expert in hardware  at this level sorry :) i only try to learn about it.
Title: Re: Gate array decapped!
Post by: pelrun on 21:45, 15 April 16
You get one transistor everywhere there is a thin red line crossing one of the green squares - either an N-fet or a P-fet depending on how the square is doped. That gives you two transistors per square, sharing one pin. The red line is the gate, and the green areas to the sides are the source/drain (the fets are symmetrical, it doesn't matter which you call source or drain.) The red 'wire' is thinner in the transistor area because that affects the properties of the transistor; it's larger elsewhere to provide enough area to attach wires to. If you read the start of the patent I posted earlier, it describes this in a fairly straightforward manner.


As you've guessed, where the vcc/gnd bus bars are connected to the transistors shows up as vertical edges - there's an insulating layer between the top metal layer and the polysilicon below, and there are holes in this layer to allow the metal and polysilicon to touch. You're literally seeing the edges of the holes, as the metal layer drops into the hole and back up the other side.
Title: Re: Gate array decapped!
Post by: gerald on 16:03, 16 April 16
A good picture is better than thousand words :
Here is a inverter, implemented in the gate array. This is the 1st one on the 16MHz input clock path
 [ You are not allowed to view attachments ]
The metal on the left of the output is the input going somewhere else.
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 20:02, 16 April 16
It is extremely interesting, for somebody like me, too see these kind of jobs done and interpreted. A great, great opportunity to learn a lot  :-*
Title: Re: Gate array decapped!
Post by: robcfg on 21:18, 16 April 16
This is top notch stuff! Thanks @gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) !


Is it safe to assume that every other inverter on the gate array should look exactly the same as this one?
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 21:35, 16 April 16
It should be possible, once characterized the main functional units, to create a program to annotate all of them, right? You would probably need to "teach" it with a few examples, but it should work, since it is essentially the same I do to create a 3D structure from 2D projections of a particular protein complex. Although the reallity is more complicate in my case (you select a bunch of 2D projections rotated in different angles, then a 2D fourier transform is computed for all the projections, the you group them in class averages based on their fourier transform, and then you reconstruct the 3D model in the fourier space) a similar approach would probably work here, specially considering that we do not have different rotations but always the same view, something that simplifies the process a lot. I am the biologist in my lab, I work in the biochemical part preparing the samples and not coding the software, but I am convinced that it should really work. On the other hand, maybe there is something like this already, I do not know about reverse reverse engineering. In any case, if somebody would like to implement something like this I can submit you guys a tons of paper discussing the algorithms, everything is open source.

Title: Re: Gate array decapped!
Post by: gerald on 22:02, 16 April 16
Is it safe to assume that every other inverter on the gate array should look exactly the same as this one?
More or less  ;D
- The connection of the input / output port can change.
- There is also a strong inverter (made of 2 GA cells)

Title: Re: Gate array decapped!
Post by: Gryzor on 15:58, 18 April 16
Yes, but I guess that even with a program doing the grunt work you'd still need to double-check manually... not exactly easy :D
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 17:10, 18 April 16
It would actually be a titanic task for something like the ASIC in the Plus, even with the help of a proper tool  :-X . All the others would be very difficult as well...  :-X
Title: Re: Gate array decapped!
Post by: dragon on 17:43, 18 April 16
It would actually be a titanic task for something like the ASIC in the Plus, even with the help of a proper tool  :-X . All the others would be very difficult as well...  :-X

Not necesarilly. The amstrad ciruit reencarnarion is not made from 0, is acumulative, it have changes because change in tecnology, but apart from that, if you pick the 40007 circuit, the 48000 is the same but adapted to a diferent tecnology. I supposed the 40010 was simply the same circuit rearranged to avoid the heat problems in 40008 using the same  gate array with more cells.

The preasic  probably have these circuit of 40010 embbed+ the other chips emulated connected with the outs pins of the old desing of the gate array.

The asic plus probably have  a copy of the schematic of the preasic inside but with the new features add in it.

Thats the resason in amstrad not made a 16bit computer. 16bit need made all from 0 and two years of work. but the plus, is the same with add logic.So mostly of the job is done in a few monts..


I thinks all time the grey bars are the the poly jeje, i read it at reverse .
Title: Re: Gate array decapped!
Post by: Munchausen on 18:17, 18 April 16
Yeah, this has been done before and is possible. See for example the acorn tube ULA for which a replacement has been produced by image processing and some manual intervention on scans of the Ferranti ULA design: Tube ULA Reverse Engineering - stardot.org.uk (http://stardot.org.uk/forums/viewtopic.php?t=8539)

The Amstrad ICs are harder because you are working from a photo of the actual chip, but the principle is the same: The software tries to match the connections for each gate, but some manual intervention will be required. Those guys actually developed their own software for the job...
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 18:33, 18 April 16
Not necesarilly. The amstrad ciruit reencarnarion is not made from 0, is acumulative, it have changes because change in tecnology, but apart from that, if you pick the 40007 circuit, the 48000 is the same but adapted to a diferent tecnology. I supposed the 40010 was simply the same circuit rearranged to avoid the heat problems in 40008 using the same  gate array with more cells.

The preasic  probably have these circuit of 40010 embbed+ the other chips emulated connected with the outs pins of the old desing of the gate array.

The asic plus probably have  a copy of the schematic of the preasic inside but with the new features add in it.

Thats the resason in amstrad not made a 16bit computer. 16bit need made all from 0 and two years of work. but the plus, is the same with add logic.So mostly of the job is done in a few monts..


I thinks all time the grey bars are the the poly jeje, i read it at reverse .

If it is additive and not a redesign from the scratch then it would be actually very doable! With a lot of work, but very doable :). That would be actually great. Do not ask me why, but I always assumed that the ASIC from the Plus was a design not based in accumulative approach. I also thought that this was the main cause of the "bugs" it has. Great to know that it is not the case  :D
Title: Re: Gate array decapped!
Post by: dragon on 18:43, 18 April 16
Yeah, this has been done before and is possible. See for example the acorn tube ULA for which a replacement has been produced by image processing and some manual intervention on scans of the Ferranti ULA design: Tube ULA Reverse Engineering - stardot.org.uk (http://stardot.org.uk/forums/viewtopic.php?t=8539)

The Amstrad ICs are harder because you are working from a photo of the actual chip, but the principle is the same: The software tries to match the connections for each gate, but some manual intervention will be required. Those guys actually developed their own software for the job...

I remember read steve gane(the asic harware developer), tell proably it have the tapes in sun of the asic in some place.But tell he drop it jeje. probalby he simply uses the lsi logic software to do that.

Anyway, what ula model the arcon bbc have?.Can this software works with the 40007?(5000r ula series)

If it is additive and not a redesign from the scratch then it would be actually very doable! With a lot of work, but very doable :) . That would be actually great. Do not ask me why, but I always assumed that the ASIC from the Plus was a design not based in accumulative approach. I also thought that this was the main cause of the "bugs" it has. Great to know that it is not the case  :D

If i remember correctly. the bugs are in the new features, but not in the old cpc part :) . And i remember read about the preasic in the google groups the preasic principally is  made to subsitute the obsolete old ram access to the old ram,so  amstrad can  use the new ram chips in preasic and later in the asic.

A little advantage we know a little part of the circuit.(the acid  patent in the plus part).
Title: Re: Gate array decapped!
Post by: gerald on 18:45, 18 April 16
If it is additive and not a redesign from the scratch then it would be actually very doable!
Unlikely to be additive, even for the 40008 to 40010. 5BTW, looking at LSI reference, the 40008 uses a bigger array)
The usual design is schematic entry, then the manufacturer tool suite place it where it fits on the gate array.

Toying with degate[nb]Sharp eyes will spot two different implementation of the inverter[/nb] :
 [ You are not allowed to view attachments ]

Title: Re: Gate array decapped!
Post by: dragon on 19:13, 18 April 16
And why do you think the 40008 have bigger array gerald?. The pdf say it have  1332 blocks(3130), and the other 1722(3170).

Is bad the numeration in the cpcwikiparts or so?.

Amstrad part numbers - CPCWiki (http://www.cpcwiki.eu/index.php/Amstrad_part_numbers)

Or you say simply is bigger?.(And i trasltate bad for english) :).
Title: Re: Gate array decapped!
Post by: gerald on 20:47, 18 April 16
And why do you think the 40008 have bigger array gerald?. The pdf say it have  1332 blocks(3130), and the other 1722(3170).
Simply because the number of cell in the 40010 picture matches the LL3130 (18*74=1332)  ;)
Title: Re: Gate array decapped!
Post by: dragon on 21:16, 18 April 16
Oh men, this is really strange, i open the service manual of 664 and 6128 in the wiki.

In the ic says "amstrad 40010 hsg3130 or 3170".

All the info in the wiki was wrong. Exist two version of the 40010?

The pin compatible are the 40007 and the 40008 no?, not the 40008 and the 40010.

If it the 40007 and the 40008, are the two ferranti ics.And 40010 are provide with the same circuit in the two distints internal array chips depending of the disponibility?.
Title: Re: Gate array decapped!
Post by: robcfg on 21:25, 18 April 16
40008 and 40010 are pin compatible, the 40007 is not
Title: Re: Gate array decapped!
Post by: gerald on 21:33, 18 April 16
Oh men, this is really strange, i open the service manual of 664 and 6128 in the wiki.

In the ic says "amstrad 40010 hsg3130 or 3170".

All the info in the wiki was wrong. Exist two version of the 40010?

The pin compatible are the 40007 and the 40008 no?, not the 40008 and the 40010.

If it the 40007 and the 40008, are the two ferranti ics.And 40010 are provide with the same circuit in the two distints internal array chips depending of the disponibility?.
40008 and 40010 are pin compatible, the 40007 is not
If these two picture are not fake, 40008 is 40007 compatible

http://www.cpcwiki.eu/imgs/6/69/CPC464_PCB_Top_%28Z70200_MC0002D%29.jpg (http://www.cpcwiki.eu/imgs/6/69/CPC464_PCB_Top_%28Z70200_MC0002D%29.jpg)
http://www.cpcwiki.eu/imgs/9/92/CPC464_PCB_Top_%28Z70200_MC0002D%29_GA40008.jpg (http://www.cpcwiki.eu/imgs/9/92/CPC464_PCB_Top_%28Z70200_MC0002D%29_GA40008.jpg)

And then we may think of 2 versions of 40010  :D

Title: Re: Gate array decapped!
Post by: dragon on 21:59, 18 April 16
Yes i think maybe we are wrong all time, comparing the font letter in the pictures of the 40007 and 40008.Are the same, and the two serial numbers begin with F, and add in the service manual in the 40007 motherboard draw say ferrat ic.


But i think this can be a problem, i remember reading in the spectrum ula book page took several ics to decapped it. It appears the ferranti ics are very sensible. And in the other hand  i remember robcfg telling 40007 was broken in the process....

So i think  maybe the 40008 can broke easily as the 40007 in the process.

Oh, you have compared the details in 40007 gerald. Maybe the have different rervisions to ?.

In the first picture a 464 have 40007-4 Fxxxx
But in the second picture the cpc have 40007-4x fxxxx

File:CPC464 PCB Top (Z70100) GA40007-4.jpg - CPCWiki (http://www.cpcwiki.eu/index.php/File:CPC464_PCB_Top_%28Z70100%29_GA40007-4.jpg)
http://www.cpcwiki.eu/imgs/0/0d/CPC464_Z70100_MC0001A_PCB_Top.jpg (http://www.cpcwiki.eu/imgs/0/0d/CPC464_Z70100_MC0001A_PCB_Top.jpg)

Or is part of the serial number?.
Title: Re: Gate array decapped!
Post by: gerald on 22:42, 18 April 16
Oh, you have compared the details in 40007 gerald. Maybe the have different rervisions to ?.

In the first picture a 464 have 40007-4 Fxxxx
But in the second picture the cpc have 40007-4x fxxxx

File:CPC464 PCB Top (Z70100) GA40007-4.jpg - CPCWiki (http://www.cpcwiki.eu/index.php/File:CPC464_PCB_Top_%28Z70100%29_GA40007-4.jpg)
http://www.cpcwiki.eu/imgs/0/0d/CPC464_Z70100_MC0001A_PCB_Top.jpg (http://www.cpcwiki.eu/imgs/0/0d/CPC464_Z70100_MC0001A_PCB_Top.jpg)

That's the date code
8428 mean year 1984 week 28
8436 mean year 1984 week 36
Title: Re: Gate array decapped!
Post by: robcfg on 23:36, 18 April 16
If these two picture are not fake, 40008 is 40007 compatible

http://www.cpcwiki.eu/imgs/6/69/CPC464_PCB_Top_%28Z70200_MC0002D%29.jpg (http://www.cpcwiki.eu/imgs/6/69/CPC464_PCB_Top_%28Z70200_MC0002D%29.jpg)
http://www.cpcwiki.eu/imgs/9/92/CPC464_PCB_Top_%28Z70200_MC0002D%29_GA40008.jpg (http://www.cpcwiki.eu/imgs/9/92/CPC464_PCB_Top_%28Z70200_MC0002D%29_GA40008.jpg)

And then we may think of 2 versions of 40010  :D


Damn! You're right! I've taken a look at the other boards, and 40007 and 40008 GAs go in the same socket and only 40010 goes in the other one.


Also, I've noticed an error in the Grimware's Gate Array page (http://www.grimware.org/doku.php/documentations/devices/gatearray), which says that the CPC664 had a 40008 GA. If you take a look at our pictures, the 664 come with a 40010 GA, and only the later 464 and earlier 6128 have slots for the different GA models.


It seems that the pin compatible ones are indeed 40007 and 40008.


And we thought we knew a lot about the CPC...  :D
Title: Re: Gate array decapped!
Post by: dragon on 00:21, 19 April 16
I have a theory how we can distinguis the 40010-a and 40010-b

Looking to the die, the internal number are different fron the code encapsulated, except by the "36 AA" is in the lsi copyright part.

I revised the picures of all boards, it appears all cpc have 36 AA  and other have "37 AA"

The other numbers vary from board in board, but these part have only two types and are continuosly numbers as the numbers in the datasheet.

I was think all my life the 664 has epecial and it have the 40008 jaja but hey it have a 37aa code.

In the other hand i think only 664 and first 6128(464 i not sure).mount the 3170. Maybe they discover later the circuit enter in a low cost gate array 3130.And swap to it or so.

PD:seriusly, i have found the gate array original schematic but used in the pc 1512 in a museum! :)

Objects (http://www.nationalmediamuseum.org.uk/scim/online_science/explore_our_collections/objects/index/smxg-8091148)

This confirmed these corner are part number and not serial number.
Title: Re: Gate array decapped!
Post by: gerald on 13:43, 19 April 16
I have a theory how we can distinguis the 40010-a and 40010-b

Looking to the die, the internal number are different fron the code encapsulated, except by the "36 AA" is in the lsi copyright part.

I revised the picures of all boards, it appears all cpc have 36 AA  and other have "37 AA"

The other numbers vary from board in board, but these part have only two types and are continuosly numbers as the numbers in the datasheet.

I was think all my life the 664 has epecial and it have the 40008 jaja but hey it have a 37aa code.

In the other hand i think only 664 and first 6128(464 i not sure).mount the 3170. Maybe they discover later the circuit enter in a low cost gate array 3130.And swap to it or so.
Good find.
So we can externally identify the two 40010
 - one using LL3170 and marked with 37AA ( appeared on 664 ?)
 - one using LL3130 and marked with 36AA ( most of others ?)

Now we need to fix documentation referring the 40008 as pin compatible with the 40010s (@grim can you update the grimware ?)
Title: Re: Gate array decapped!
Post by: dragon on 14:33, 19 April 16
Maybe is a good idea made the grimware rasterization test to one gate array aa37?.

Maybe we can  view a suprise or not :) . but i not have these gate array.

Also cpcmaniaco i remember have 664 schneiders maybe robcfg can take a look at it to confirm they have aa37. And more 464 and 6128 1stgen.

Its only question of find it in a 464, and compare cpc serial dates with the 664. If not exist in the 464, it came out in 664, if 464 date are early that 664, then go out in 464.

well in the wiki the first 464 with double slot is z70200 mc0001a: File:Z70200 MC0001A TOP.JPG - CPCWiki (http://www.cpcwiki.eu/index.php/File:Z70200_MC0001A_TOP.JPG)

And the first 664 is mc0005a z70205, so 464 was prepared for the 400010 early 664 came out.But thats not mean it mount aa37, because amstrad can put 40008 first to eliminate stock existences. And when all 40007/40008 are put, then maybe put the aa36.

http://www.cpcwiki.eu/imgs/f/f2/CPC664_PCB_Top.jpg (http://www.cpcwiki.eu/imgs/f/f2/CPC664_PCB_Top.jpg)

One interesting think apart. The ic 125. This ic was ferranti in 464 and then change in the cpc doble slot gate array(to thosiba lsi partner), that proably means amstrad broke with ferranti and they not buy  it more chip, and these 40007 are rest of stock. And at the same time the z80 change to sgs. It is connected to xtal part of the 16mhz clock logic generated by the quarz to  the gate array.
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 16:41, 19 April 16
I see that is still possible to buy the 40489 ASIC as spare part (the ASIC from the Plus). It is expensive, around 75 euros per unit, but maybe we could try to decap this guy as well. How do you feel about that? We would probably need to buy two or three but it could be worth it. I would happily contribute to buy them.

Semiconductor: 40489 - AMSTRAD-IC GATE ARRAY - UK (GBP) (http://www.donberg.co.uk/descript/4/40489.htm)
Title: Re: Gate array decapped!
Post by: robcfg on 16:45, 19 April 16
We already sent one asic to Sean. We just need to wait him to decap and make the pictures out of it :D
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 16:49, 19 April 16
Jesus, I forgot!  :picard: With the ASICs from the normal CPC I forgot the other one!  :D
Title: Re: Gate array decapped!
Post by: MaV on 16:52, 19 April 16
If he has problems decapping the one ASIC and we need another one, I'll be happy to contribute as well!
Title: Re: Gate array decapped!
Post by: robcfg on 16:53, 19 April 16
Thank you very much!


He described the asic as being... toasty, but hopes we can get good pictures out of it.
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 17:11, 19 April 16
Let´s see, but yes, if more than one is needed here we are!  :D
Title: Re: Gate array decapped!
Post by: TotO on 17:40, 19 April 16
It is less expansive to buy a brand new GX4000 than an ASIC chip only...  :picard:
Sellers practice excessive prices... (they got them for around 10$ each)
Better to not buy to them, else the price will continue to grow!
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 18:31, 19 April 16
That is certainly a good point as well, a second hand GX4000 is quite cheap, the problem is that you feel bad for it unless you know that it is already broken but with the ASIC still fine  :)
Title: Re: Gate array decapped!
Post by: dragon on 21:39, 19 April 16
Ohh,i found another mystery.

In the 464 service manual the ferranti ic 125 is called "40008" ¿?¿?¿?
In the 6128 with the two gate array options the thosiba chip  in ic 125 is called "40008/A" But it not have the same function logic of the ferranti ic.

An then i found this  strage book about 80 computers called" "Electronic Dreams: How 1980s Britain Learned to Love the Computer"

it speak about amstrad a few pages, and it offers a different point of view about amstrad ferranti history.

Normally in the books it say. The problem with the ferranti are the pads are not connected to the ic, book this book tell in perry words. The amstrad team visited ferranti factory.The put the chip, and they discover it not work. And the problems was the onboard crystall oscilator won't oscillate, so it search and found a second source in italy instead of wait the fix from ferranti (the sgs aa37 italy)?

Maybe the 40008 have the fix from ferranti ?.


Title: Re: Gate array decapped!
Post by: gerald on 22:19, 19 April 16
Ohh,i found another mystery.

In the 464 service manual the ferranti ic 125 is called "40008" ¿?¿?¿?
In the 6128 with the two gate array options the thosiba chip  in ic 125 is called "40008/A" But it not have the same function logic of the ferranti ic.
These are just Amstrad part number that repair services have to use to get part from Amstrad.
Amstrad put these number on they own designed part, but the the 40008 is just a 'standard' 4xNAND ic.
Title: Re: Gate array decapped!
Post by: dragon on 14:18, 20 April 16
Well i can fail, jeje the history around gate array in the history books don't is very clear.

One question robcfg. Can be a posbility of decapped a 40010 aa37?.
Title: Re: Gate array decapped!
Post by: robcfg on 14:46, 20 April 16
Sure, we'll be sending another 40007 and a 40008 to Sean for decapping, so if you have have a 40010 AA37 we can send them together.
Title: Re: Gate array decapped!
Post by: TotO on 14:56, 20 April 16
Sure, we'll be sending another 40007 and a 40008 to Sean for decapping, so if you have have a 40010 AA37 we can send them together.
I have some differents 40010... May be the AA37 too.
Title: Re: Gate array decapped!
Post by: dragon on 15:25, 20 April 16
Sure, we'll be sending another 40007 and a 40008 to Sean for decapping, so if you have have a 40010 AA37 we can send them together.

Oh i not have it. My 6128  is a pre-asic, 1 464 have 40010 36aa (the board is in the the wiki), and the other have one with heatshink so probably is a 40007.

I search it in the web to buy one but all appears be 36aa :(.
Title: Re: Gate array decapped!
Post by: TotO on 15:28, 20 April 16
Don't search to buy... I should have one. (or buy it to me!  :laugh: )
Title: Re: Gate array decapped!
Post by: dragon on 15:47, 20 April 16
Mmm, is a rare chip, this is my offer:

(http://historiasdelahistoria.com/wordpress-2.3.1-ES-0.1-FULL/wp-content/uploads/2012/02/100-trillion-dolars.jpg)

 8)

Anyway can you mount it and try the grimware test first? is the last voluntair of the ic in her testament after we sacrafice it to the vulcan.
Title: Re: Gate array decapped!
Post by: Higgy on 14:27, 21 April 16
Hi guys,

I have a 40010 18509 37AA 'Made in Italy' which is dead. Is it of any use for this?  (this was in a 6128)

I would get the 'white screen & black borders' and the screen would continuously scroll/flicker upwards (or was it downwards).
Anyway I tried swapping CPU, PAL and then swapped the 40010 to a known working 36AA and then it worked  ;D   Just waiting for a replacement now. 174193
Title: Re: Gate array decapped!
Post by: dragon on 15:29, 21 April 16
Yes, is the teorically hsg3170 gate array. aa37 always are made in italy, and the part number begins with 18.aa36(the decapped) not have italy mark(as if it is made in other site) and part number begins with more far upper number.

What motherboard version you have in the 6128 the first release?.For stadistics.

Title: Re: Gate array decapped!
Post by: robcfg on 16:12, 21 April 16
Hi @Higgy (http://www.cpcwiki.eu/forum/index.php?action=profile;u=1486) !


Even if it's broken it may serve its purpose of being decapped and pictured. So it would be nice if you could send it to me to be included in the next batch.


Please, send me a PM so we can work the details.


Cheers,
Rob
Title: Re: Gate array decapped!
Post by: Higgy on 19:56, 21 April 16
@dragon (http://www.cpcwiki.eu/forum/index.php?action=profile;u=251) - hopefully this pic works.

Part no. Z70210

 [ You are not allowed to view attachments ]
Title: Re: Gate array decapped!
Post by: dragon on 23:39, 21 April 16
Sounds like its the first motherboard MC0009A  so at the momet only this board and cpc 664 mount these gate array type.
Title: Re: Gate array decapped!
Post by: Higgy on 00:50, 22 April 16
From my picture the letter is hidden but looks like an A. When I open her up again for the 40010 replacement I will check.

The other motherboard is a MC0020C
Title: Re: Gate array decapped!
Post by: MacDeath on 03:01, 22 April 16
Mmm, is a rare chip, this is my offer:

(http://historiasdelahistoria.com/wordpress-2.3.1-ES-0.1-FULL/wp-content/uploads/2012/02/100-trillion-dolars.jpg)

 8)

Anyway can you mount it and try the grimware test first? is the last voluntair of the ic in her testament after we sacrafice it to the vulcan.
this was just your three cents...
Title: Re: Gate array decapped!
Post by: dragon on 03:23, 22 April 16
Really  is not in circulation from varius years ago is a colecionist billete because are the most bigger number expedited in the world.

So it cost used around the price of the ebay  40008 and uncirculated can cost the doble. :). It have a curius history.
 
I never view one phisically. But is the bigger number in the world, tecnically you can say you are multimillonary a very low cost. Alan sugar style.
Title: Re: Gate array decapped!
Post by: seanb on 12:58, 22 April 16
I bought a gold version of that note of ebay for a friend as a joke once.
Title: Re: Gate array decapped!
Post by: robcfg on 14:03, 25 April 16
Hi guys!


I just uploaded a new picture to the Gate Array page. It's the 40010 GA with the metal layer removed.


Sean also sent me a 16000x16000 picture of the 40010 metal layer, but it's way too big for the wiki...  ;D


If anyone is interested (maybe @gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) ) send me a PM for the link.


Cheers,
Rob
Title: Re: Gate array decapped!
Post by: dragon on 15:21, 25 April 16
I understand now why the s(from sgs) are lost in the musseum  picture, it lost when metal layer are removed.

If picture is bigger too the wiki, simply upload it to mega, and put the link in the wiki.More easy.

Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 18:08, 25 April 16
I was checking the high res pictures now and they are really a beauty  :o They look like a huge carpet  :laugh:
Title: Re: Gate array decapped!
Post by: TFM on 18:10, 25 April 16
A good picture is better than thousand words :
Here is a inverter, implemented in the gate array. This is the 1st one on the 16MHz input clock path
 [ You are not allowed to view attachments ]
The metal on the left of the output is the input going somewhere else.


So this is where Tron lives?

Title: Re: Gate array decapped!
Post by: robcfg on 18:53, 25 April 16
Heh...


I remember as kid watching the movie and then typing "TRON" on my CPC. I got quite shocked that it worked, hehe  :D
Title: Re: Gate array decapped!
Post by: TotO on 00:34, 29 April 16
I have only one 40010 37AA (Made in Italy) chip.  :-\
Title: Re: Gate array decapped!
Post by: Higgy on 09:50, 29 April 16
I will be posting a 37AA to Rob  ;D 108
Title: Re: Gate array decapped!
Post by: dragon on 14:23, 29 April 16
I have only one 40010 37AA (Made in Italy) chip.  :-\

Its a strange species, in extintiction with the 40008.
Title: Re: Gate array decapped!
Post by: robcfg on 13:38, 04 May 16
Hello everyone!


Sean sent me a first picture of the 40489 ASIC (https://www.dropbox.com/s/20qkelnr0im21wn/amstrad3_metal.jpg?dl=0). It's not useful for getting anything out of it, but it's a first step  8)


The whole thing is covered by a brown plastic layer that Sean hopes will get away with nitric acid.


This one took 576 pictures...  :o


He will be taking 20x pictures soon.
Title: Re: Gate array decapped!
Post by: dragon on 13:55, 04 May 16
Thanks robcfg, so the  black hole are plastic?.

The chip appears divided in some parts, i think one of the type zones can be the asic ram. I not sure if it is a gate array or a asic. Anyway it not appear to have  name constructor on it

In service manual have note it have 10000 logic gates. Is 10x more that the gate array.

In the other hand can be more zoom in the future to the preasic too?.
Title: Re: Gate array decapped!
Post by: robcfg on 14:01, 04 May 16
Actually, the plastic is the brown square that cover almost everything.


Also, yes, several parts can be seen. I bet that the 16 identical areas are the sprites' ram.


Sean told me he'll be taking higher resolution pictures, but keep in mind that he has to take thousands of pictures, and then compose them together so be patient  ;)
Title: Re: Gate array decapped!
Post by: dragon on 14:15, 04 May 16
O.k robcfg, i think tha name chip is in a corner, but is to little to see it. With lucky we can view it at 16x later :) . Or simply tell sean take note of the code.

The chip appeared very well structurated.Steve gane made a good job.k

as you say, the chip have 16 squares 8 in upper and 8 in down part.+ 1 extra maybe to control it 1square=1sprite?

Or best, the two extra squares are connected to  the outside directly. Maybe is another thing as the dma sound part or so.

ah, i don't see it in the movil XD, but i can view it in pc the ic code is "c838002"
Title: Re: Gate array decapped!
Post by: gerald on 20:09, 04 May 16
Hello everyone!


Sean sent me a first picture of the 40489 ASIC (https://www.dropbox.com/s/20qkelnr0im21wn/amstrad3_metal.jpg?dl=0). It's not useful for getting anything out of it, but it's a first step  8)


The whole thing is covered by a brown plastic layer that Sean hopes will get away with nitric acid.


This one took 576 pictures...  :o


He will be taking 20x pictures soon.
Higher resolution is definitively needed if we want to get something out of it  ;)
Title: Re: Gate array decapped!
Post by: TFM on 21:19, 04 May 16
Sean sent me a first picture of the 40489 ASIC (https://www.dropbox.com/s/20qkelnr0im21wn/amstrad3_metal.jpg?dl=0). It's not useful for getting anything out of it, but it's a first step  8)


One can clearly see the sprite RAM, tooks lots of space...
Title: Re: Gate array decapped!
Post by: dragon on 22:15, 04 May 16
who is using more space for 8 sprites commodore ic or amstrad?.

Commodore 8565 VIC-II (http://visual6502.org/images/pages/Commodore_8565_die_shots.html)


Title: Re: Gate array decapped!
Post by: arnoldemu on 22:37, 04 May 16
who is using more space for 8 sprites commodore ic or amstrad?.

Commodore 8565 VIC-II (http://visual6502.org/images/pages/Commodore_8565_die_shots.html)
commodore reads sprites from ram so no sprite data on the ic.

asic has sprites on the ic. So amstrad uses much more!
Title: Re: Gate array decapped!
Post by: TFM on 23:52, 04 May 16
So for the ASIC II...
- 256 sprite colors instead of 16
- 32 sprites instead of 16


Just in case there will be a 7128 Plus or something like that.  ;)
Title: Re: Gate array decapped!
Post by: dragon on 01:41, 05 May 16
I think i more probable a gate array plus.

Because the gate array is in soket so is cuestion of swap. In the rest you need unsolder/solder...

You can made a gate array with plus features.
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 13:00, 05 May 16
The Plus ASIC looks really pretty and well organized. I must confess that I was not expecting something like that, so simmetric. Actually, I was almost sure that it would be a much less organized design, where you could clearly see the CPU in a corner, some memory somewhere else, a section for the Plus features... much more like the PS4 APU .
Title: Re: Gate array decapped!
Post by: robcfg on 13:45, 05 May 16
I'd like to thank @Higgy (http://www.cpcwiki.eu/forum/index.php?action=profile;u=1486) because the 37AA 40010 chip just arrived and will be on the next batch for decapping.


It will be nice to see if they have any difference.


So, thank you very much!  8)
Title: Re: Gate array decapped!
Post by: Higgy on 16:51, 05 May 16
No problem. Glad the timing worked out and I saw it would be useful. Otherwise it would have probably ended up in the bin  :doh:

Retro communities are a nice friendly bunch  so if I can help I like to.
It is also fun reading and learning about new systems. Next job is to add a reset switch and remove my Type 2 CRTC  :o
Title: Re: Gate array decapped!
Post by: arnoldemu on 11:10, 06 May 16
No problem. Glad the timing worked out and I saw it would be useful. Otherwise it would have probably ended up in the bin  :doh:

Retro communities are a nice friendly bunch  so if I can help I like to.
It is also fun reading and learning about new systems. Next job is to add a reset switch and remove my Type 2 CRTC  :o
send the type 2 for decapping! :)
Title: Re: Gate array decapped!
Post by: dragon on 13:33, 06 May 16
Quote from: arnoldemu link=topic=11888.msg125934#msg125934 dcpce=1462522241
send the type 2 for decapping! :)

I quote you to read you

(Expansion quote you know lol).

I can donate a broken cartridge board with a broken acid, it dies time ago in the process of transform it to a socket cartridge when c4cpc not exist. Probably it burn lol.Anyway the board have damaged too.

What other  chips have unkown die . pcw and  last spectrum anstrad made?. I think the autor of zx spectrum book not decapped it, it stop in amstrad.
Title: Re: Gate array decapped!
Post by: Munchausen on 22:18, 06 May 16
The Plus ASIC looks really pretty and well organized. I must confess that I was not expecting something like that, so simmetric. Actually, I was almost sure that it would be a much less organized design, where you could clearly see the CPU in a corner, some memory somewhere else, a section for the Plus features... much more like the PS4 APU .

The CPU and RAM are actually still separate with the ASIC. I didn't actually realise that the sprite RAM was on board, I'd guess that might have been quite expensive. I wonder if that was just the cheapest way to do it while maintaining backwards compatibility (not changing the CPU timing by further RAM accesses from the "gate array", and not needing extra external RAM).

The developments in this thread are very exciting, it's always the first thread I check back to at the moment!
Title: Re: Gate array decapped!
Post by: TotO on 22:43, 06 May 16
Is really useful to send CRTC for decaping?
They are not CPC special circuits.
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 23:43, 06 May 16
The CPU and RAM are actually still separate with the ASIC. I didn't actually realise that the sprite RAM was on board, I'd guess that might have been quite expensive. I wonder if that was just the cheapest way to do it while maintaining backwards compatibility (not changing the CPU timing by further RAM accesses from the "gate array", and not needing extra external RAM).

The developments in this thread are very exciting, it's always the first thread I check back to at the moment!

Thank you! I knew that the RAM and the Z80 were outside, but I was still expecting to see something like a "general" CPU inside among the other chips, stupid of me  :-\
Title: Re: Gate array decapped!
Post by: dragon on 00:54, 07 May 16
I read in the google groups time ago, the dma in asic is a little processor from people of amstrad. Thats because i tell if the two big square in the left near the other 8 sprites are the dma sound.

So maybe is true the asic have a cpu in some form :).
Title: Re: Gate array decapped!
Post by: gerald on 10:38, 07 May 16
Is really useful to send CRTC for decaping?
They are not CPC special circuits.
Not CPC specific, but different behaviour of different version when used on CPC.
Could still be interesting to have all type reverse engineered at some point.
Title: Re: Gate array decapped!
Post by: TotO on 14:03, 07 May 16
Sure, while the guy is OK to do it for all the IC sent.  :)
Title: Re: Gate array decapped!
Post by: dragon on 14:24, 07 May 16
Fortunly we live in a epoque when you can made 500 pictures at not cost.


Inagine decapped the asic in the 80 with analogue photography.


Hi man of kodak shop i need send to reveal 500 pictures of a chip lol. (A dolar apear in eyes of man).
Title: Re: Gate array decapped!
Post by: Munchausen on 16:38, 07 May 16
Thank you! I knew that the RAM and the Z80 were outside, but I was still expecting to see something like a "general" CPU inside among the other chips, stupid of me  :-\

Actually you may be right, it does have to do something like decode register -> do something, with RAM access etc too, so it may somewhat resemble a CPU.
Title: Re: Gate array decapped!
Post by: dragon on 21:26, 14 July 16
Just for curiosity any news obtaining the 40010 schematic or the other ics?
Title: Re: Gate array decapped!
Post by: robcfg on 13:04, 13 September 16

Hi guys!


I uploaded the 40010, PreASIC and ASIC 20x pictures to Mega.


The 40010 pictures are jpg and the 40226 and 40489 are in deep zoom format as they are otherwise unmanageable.


I included the OpenSeaDragon deep zoom viewer and created convenient html files. For viewing them from your disk, I recommend FireFox as Chrome is too picky with the data origin.


40010 Metal Layer: https://mega.nz/#!hkEwxLjA!ACfSH1p6Cp7QkbkdcA3NmPPB_bIdtaSz2TQdBmCt5ss (https://mega.nz/#!hkEwxLjA!ACfSH1p6Cp7QkbkdcA3NmPPB_bIdtaSz2TQdBmCt5ss)
40010 Metal Layer Removed: https://mega.nz/#!E0ljlKoK!nErCPUcuzMt8smAj_NWjx8wJmrIyL67qqdxx5Dz1eBQ (https://mega.nz/#!E0ljlKoK!nErCPUcuzMt8smAj_NWjx8wJmrIyL67qqdxx5Dz1eBQ)
40226 and 40489 Deep Zoom Images: https://mega.nz/#!o0dE1ATL!5eHANmjOS-aTHR2tiN0hLZw0AGeLvInTIcca-IooZJQ (https://mega.nz/#!o0dE1ATL!5eHANmjOS-aTHR2tiN0hLZw0AGeLvInTIcca-IooZJQ)


@Gryzor (http://www.cpcwiki.eu/forum/index.php?action=profile;u=1) : I sent you an email a while ago, but seems to have been lost in the tides of time. Would it be possible to upload the Deep Zoom Images and the viewer to the wiki?If it's possible, I'd like to put proper credits first to the html files but you can try with the files I uploaded.

Just for curiosity any news obtaining the 40010 schematic or the other ics?


@gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) was working on it. No easy task, so please be patient  ;)
Title: Re: Gate array decapped!
Post by: Gryzor on 14:32, 13 September 16
Hey mate,


I don't seem to have that email, this is the first time I hear about Deep Zoom :D But... are we talking about the 1.4GB file? I think it's a bit too much, though if enough people are interested I'll upload it to the server; not through the wiki though.
Title: Re: Gate array decapped!
Post by: gerald on 18:54, 13 September 16
@gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) was working on it. No easy task, so please be patient  ;)
Most of the job is done. I just need to check it against real HW.
Preliminary schematic attached.
I have VHDL code ongoing, but in standby for the last 2 weeks.
Title: Re: Gate array decapped!
Post by: Duke on 19:35, 13 September 16
Impressive work @gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) . And thanks @robcfg (http://www.cpcwiki.eu/forum/index.php?action=profile;u=4) for the images.
Title: Re: Gate array decapped!
Post by: Arnaud on 19:53, 13 September 16
Most of the job is done. I just need to check it against real HW.
Preliminary schematic attached.
I have VHDL code ongoing, but in standby for the last 2 weeks.

You can directly translate the electronic shematic in VHDL ?
It's rather different from FPGAmstrad which is an adaptation of java emulation with Javacpc or it's finally the same "code" ?

Title: Re: Gate array decapped!
Post by: gerald on 20:12, 13 September 16
You can directly translate the electronic shematic in VHDL ?
Reverse engineering have been done with degate. While it is supposed to generate a vhdl model of the 'extracted' design, it is rather buggy and did not let me add proper hierarchy to the design, which makes it unreadable. It has also some other bugs that make me use the old paper and pencil method.
With the paper schematics, I did the pdf one in Kicad, simplifying most of the equation to make them more human readable. The original design is optimised by using polarity optimisation wherever it's possible. This help reducing the number of transistors but make comprehension difficult.

It's rather different from FPGAmstrad which is an adaptation of java emulation with Javacpc or it's finally the same "code" ?
Chances are quite low that the code is the same  ;)
The 40010 uses a lot of asynchonous tricks and these may have been implemented as synchronous logic.
Title: Re: Gate array decapped!
Post by: dragon on 22:14, 13 September 16
Reverse engineering have been done with degate. While it is supposed to generate a vhdl model of the 'extracted' design, it is rather buggy and did not let me add proper hierarchy to the design, which makes it unreadable. It has also some other bugs that make me use the old paper and pencil method.
With the paper schematics, I did the pdf one in Kicad, simplifying most of the equation to make them more human readable. The original design is optimised by using polarity optimisation wherever it's possible. This help reducing the number of transistors but make comprehension difficult.
Chances are quite low that the code is the same  ;)
The 40010 uses a lot of asynchonous tricks and these may have been implemented as synchronous logic.

You are a genius hardware guy gerald. Gate array was designed with paper and pencil method, and was reverse enginered with pencil and paper method. :).

Do you have thinking about made a gate array plus?. Compatible but with posibility of more colours in all modes.
Title: Re: Gate array decapped!
Post by: TotO on 23:21, 13 September 16
I personally expect to be able to restore the Gate Array's 64 colours original palette.
About displaying more colours per pixel, it is related to the CRTC frequency...
Title: Re: Gate array decapped!
Post by: PulkoMandy on 10:05, 14 September 16

"Restoring" the 64 colors is a matter of copy-paste (mostly in "ink registers" and "color mux" parts of the schematics, the 6th bit was removed there to save space I guess) and then finding a way to output them (we'll need 3 extra pins).More colors in all modes would be possible but tricky. There are two solutions inspired by the Thomson hardware. The first is to use 16-bit memoryt accesses, for example, 8 bit from main memory, and 8 bits from banked memory. This would not need this many changes to the Gate Array, but a major rework of the motherboard (and again, probably a chip with some extra pins). The other option is to use RAM which can perform multiple accesses in the same page very fast, as it was done in the Thomson TO8. And of course there's always the option of running everything at 8MHz to avoid all these changes.
Title: Re: Gate array decapped!
Post by: TotO on 10:15, 14 September 16
"Restoring" the 64 colors is a matter of copy-paste (mostly in "ink registers" and "color mux" parts of the schematics, the 6th bit was removed there to save space I guess) and then finding a way to output them (we'll need 3 extra pins).
I have looked the schematics done by gerald yesterday evening. Yes, that will require this sort or work to be acheived. About the 3 extra pins, it is not really a problem as you can implement the 6-bit RGB DAC using resistors into the Gate Array's PCB replacement. So, the pins going to the socket doesn't change.

Title: Re: Gate array decapped!
Post by: dragon on 11:43, 14 September 16
So,probably in the Plus range they make copy paste to 12bits. :).

If more colours to Mode 0 1 and 2 is posible the best is the  method take less modificación in the motherboard.
Title: Re: Gate array decapped!
Post by: robcfg on 11:51, 14 September 16
More colors means more memory and more time needed to draw a frame.


For an adventure game it may not be a problem, but for any action game it's not going to work good.


Another thing would be to oveclock the machine...
Title: Re: Gate array decapped!
Post by: TotO on 11:53, 14 September 16
You may display more coulours w/o wasting the display or the memory by using attributes.
Title: Re: Gate array decapped!
Post by: Gryzor on 11:57, 14 September 16
I personally expect to be able to restore the Gate Array's 64 colours original palette.


Wait - what?   
Title: Re: Gate array decapped!
Post by: pelrun on 12:00, 14 September 16
WOW. This is a truly amazing piece of work, and probably the most exciting bit of base-CPC hardware documentation news in years.
Title: Re: Gate array decapped!
Post by: robcfg on 12:03, 14 September 16
You may display more coulours w/o wasting the display or the memory by using attributes.


You mean like the Spectrum?  ;D
Title: Re: Gate array decapped!
Post by: TotO on 12:07, 14 September 16
I just said that is a way to do...  ;D


Wait - what?

The INKR allow to set 6bit for the palette but only 5bit are used. By extending that, you come with a 64 colours RGB palette.
Title: Re: Gate array decapped!
Post by: Ast on 12:50, 14 September 16
I just said that is a way to do...  ;D



The INKR allow to set 6bit for the palette but only 5bit are used. By extending that, you come with a 64 colours RGB palette.

Would it be able to to that workable ?
Title: Re: Gate array decapped!
Post by: TotO on 12:52, 14 September 16
I hope... The Aleste 520 and KC Compact does that if I'm not wrong.  ;D
Title: Re: Gate array decapped!
Post by: robcfg on 13:03, 14 September 16
I was wrong on the memory requirement, as it's no new graphic mode, you have only more colours to choose from.
Title: Re: Gate array decapped!
Post by: dragon on 13:05, 14 September 16
I don't remember now if this is finally solved early sorry.

Whith the schematic finished finally what is the cause of this in 40010/b?.

(http://www.grimware.org/lib/exe/fetch.php/documentations/devices/gatearray.pal/gatearray.rasterization.timings.screenshot.png)
Title: Re: Gate array decapped!
Post by: andycadley on 13:51, 14 September 16
I just said that is a way to do...  ;D



The INKR allow to set 6bit for the palette but only 5bit are used. By extending that, you come with a 64 colours RGB palette.


It's actually something of a misnomer. The CPC was originally designed with 16 colours (using 4 bits) but later in the design it was spotted that a little hardware hackery and two extra bits to help control colour intensity could bump that up to 27 colours for very little additional cost. From a purely "digital" standpoint, it seems weird because 6-bit colour settings should give you as much as 64 colours but from a more analogue perspective the design makes sense. It's also why the "hardware colours" seem to contain a lot of duplicates.

Now you theoretically could build new hardware to "fill in the blanks" (i.e. replace some of those duplicate colours with something else) and produce a palette of 64 colours instead of 27, but the chances are fairly high that you'll get weirdness in some software which is using a different (but perfectly workable) hardware colour to get the same output as it'll suddenly start using some random other colour.

A better way of extending the palette is to forego the 6 bit colour selection method entirely, using it only as a shorthand way of changing real RGB colour registers. Which, unsurprisingly enough, is how Amstrad chose to do it on the Plus machines. The only real downside being that if you use more than 8 bit RGB values (such as the Plus 12 bit registers) you run into the problem that a Z80 can't make atomic colour changes.
Title: Re: Gate array decapped!
Post by: TotO on 14:02, 14 September 16
With only 1R, 1G, 1B, a "suposed" design without hi-Z can only produre 8 coulours (CGA). I have never read about a 16 coulours palette CPC based.
The INKR register is fully used on Alest 520 and KC Compact to handle a nice 64 coulours palette (EGA) w/o compatibility problem... Why ?
Because the hardware palette is not the software palette. The colours are remapped to match with the existing. (and I will use it)

If more coulours are required, yes you can do many things to improve that (as Pulko said)... Here is just an existing way to do.  :)
But... When you can't display more than 2/4/16 at once, a big palette is not really an advantage.
Title: Re: Gate array decapped!
Post by: arnoldemu on 15:16, 14 September 16
...
The INKR register is fully used on Alest 520 and KC Compact to handle a nice 64 coulours palette (EGA) w/o compatibility problem... Why ?
Because the hardware palette is not the software palette. The colours are remapped to match with the existing. (and I will use it)
...
On KC Compact it has the potential for 64 colours. However, the EPROM (D09) translates it to 27 colours.
Replacing the EPROM should in theory (not tested) allow 64 colours to be used.

The Aleste can do 64 colours. it has a "msx mode" and a "cpc mode" which boils down to "MAPMOD" being 1 or 0.
Again an EPROM is used (D62) which gives differing values depending on mapmod and so enables 27 or 64 colour mode. The ROM could be modified to output 64 colours in CPC mode too.

Title: Re: Gate array decapped!
Post by: TotO on 16:35, 14 September 16
Sure, the EPROM act as a look-up table to set the good software palette.
But... What about directly using the KC Compact hardware palette ? Can you access the 64 colours?
Title: Re: Gate array decapped!
Post by: arnoldemu on 22:06, 14 September 16
Sure, the EPROM act as a look-up table to set the good software palette.
But... What about directly using the KC Compact hardware palette ? Can you access the 64 colours?
No. You would need to modify the ROM or the PCB to do that.
Title: Re: Gate array decapped!
Post by: TotO on 22:18, 14 September 16
OK.  8)
Title: Re: Gate array decapped!
Post by: TotO on 22:25, 17 September 16
Thanks to gerald for his amazing work... I have started to redo the GA "core" into a CPLD using the schematic method.
The idea is to make working all things that are not related to the display. To confirm his work, I hope to be able to ring the bell!  ;D
Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 22:54, 17 September 16
I really have no time for anything until the end of the next week, but I just wanted to pop in an say that this is and amazing collaborative work guys!!  :-* :-*
Title: Re: Gate array decapped!
Post by: Executioner on 10:36, 18 September 16
It's rather different from FPGAmstrad which is an adaptation of java emulation with Javacpc or it's finally the same "code" ?

Probably not, JEMU/JavaCPC, like most other emulators, doesn't use GA shift registers and a 16 MHz pixel clock (although it probably should to be totally accurate :) )
Title: Re: Gate array decapped!
Post by: DaDMaN on 23:38, 19 September 16
Hi! One guy Ash Evans has coded a 40010 Verilog implementation based on @gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) PDF. I've been talking this afternoon with Ash about this project and this is the results.

Here is the source code:
[VeriLog] // // Amstrad CPC 40010 Gate Array implementation in Verilog. // // (http://pastebin.com/ZQyL68Hv)

 :D
Title: Re: Gate array decapped!
Post by: dragon on 23:55, 19 September 16
One cuestión is posible create a pre-sic  fpga replacement?. Knowing the other sources as crtc have verilog implementación.
Title: Re: Gate array decapped!
Post by: robcfg on 08:35, 20 September 16
It should be possible but you'll have to extract the gates and connections from the picture first (which is a huge job) and then create a vhdl or similar model.

You'd have also the problem of soldering the replacement on the board, as the preAsic has a lot of tiny pins and the replacement chip would be probably bigger.
Title: Re: Gate array decapped!
Post by: PulkoMandy on 10:47, 20 September 16
The main problems you will have with an FPGA:
- It is hard to find parts with 5V supply or even 5V-tolerant I/Os. You can't easily use a 3.3V part.
- An FPGA is volatile (like RAM), so it needs something to load code on it. Some FPGAs have a bootstrap system and they can load code from an external serial ROM.


FPGA is not "magic chip that can replace everything".


You will have better chances with fitting the gate array implementation in a CPLD (which is more like EEPROM), if you can find one large enough to fit everything.
Title: Re: Gate array decapped!
Post by: dragon on 11:19, 20 September 16
It should be possible but you'll have to extract the gates and connections from the picture first (which is a huge job) and then create a vhdl or similar model.

You'd have also the problem of soldering the replacement on the board, as the preAsic has a lot of tiny pins and the replacement chip would be probably bigger.

I not speaking about made a clone Gate by Gate of the pre-asic. If not made a own alternative  implementación of the  pre-asic  to salve the cpc dead.

Gate array in pre-asic. Have a diferent memory controller to the New ram managent. But the computer not used these  ram from factory uses the older.

So if we have a vhdl of the Gate array and we have a vhdl of the 6845 crtc. And vhdl of pal.  I speaking about only connet the three implementations between It internally  into a cpld/fpga pin compatible or to board adapter compatible.

Arnold 6 or So.


But yeah. Solder It should be a nightmare  :)
Title: Re: Gate array decapped!
Post by: gerald on 14:10, 20 September 16
The main problems you will have with an FPGA:
- It is hard to find parts with 5V supply or even 5V-tolerant I/Os. You can't easily use a 3.3V part.
- An FPGA is volatile (like RAM), so it needs something to load code on it. Some FPGAs have a bootstrap system and they can load code from an external serial ROM.


FPGA is not "magic chip that can replace everything".


You will have better chances with fitting the gate array implementation in a CPLD (which is more like EEPROM), if you can find one large enough to fit everything.
You will also have hard time tring to solder your replacement FPGA board to the 100 fine pitch footprint on the PCB. Not impossible, but a lot of trouble ahead.

Regarding CPLD,  you will have to go for the biggest. The GA does not fit a XC95144XL as it require 166DFF/Latch + glue.
It would fit the XC95288XL which is the large CPLD xilinx offer with 5V tolerant IO.

BTW, CPLD (at least xilinx ones) also need to be initialized at power up, but the configuration is stored internally and init done automatically. Bigger is the PLD, longer is the init phase.
Title: Re: Gate array decapped!
Post by: Bryce on 15:25, 20 September 16
So you'd have to modify the CPCs reset circuitry to allow for the long init time?

Regarding the soldering. It might be easiest to solder a 100pin PLCC socket to the PCB and then make a PLD solution that can plug into this?

Bryce.
Title: Re: Gate array decapped!
Post by: gerald on 19:50, 20 September 16
So you'd have to modify the CPCs reset circuitry to allow for the long init time?
May be. On early 464, the reset is short enough to prevent sampling of IO on rising edge of reset signal in my ram/flash:CF extension.
That is, the reset is released before the PLD is configured.
That's not happing on later CPC models.
That's how I discovered that init time.

Regarding the soldering. It might be easiest to solder a 100pin PLCC socket to the PCB and then make a PLD solution that can plug into this?
The pre-asic package is quite exotic to today standard. I doubt it's easy to find a socket, and custom ones cost an arm.
Title: Re: Gate array decapped!
Post by: freemac on 22:39, 20 September 16
Probably not, JEMU/JavaCPC, like most other emulators, doesn't use GA shift registers and a 16 MHz pixel clock (although it probably should to be totally accurate :) )
It's the same. FPGA is a reprogrammable CPLD. GateArray is a CPLD.
I'm currently experimenting some vhdl testbench extract from JavaCPC in order to compare vhdl (or verilog) gatearray each other.

Ok, let's catch them all : FPGA-GA - CPCWiki (http://cpcwiki.eu/index.php/FPGA-GA) (entry list)  ;)

If you succeed extracting original GateArray vhdl/verilog, you can poke me :)

Extracting CRTC1 shall interest me (CRTC0 also, but it is really too hard to implement in small FPGA yet)
Title: Re: Gate array decapped!
Post by: freemac on 22:44, 20 September 16
The main problems you will have with an FPGA:
- It is hard to find parts with 5V supply or even 5V-tolerant I/Os. You can't easily use a 3.3V part.
- An FPGA is volatile (like RAM), so it needs something to load code on it. Some FPGAs have a bootstrap system and they can load code from an external serial ROM.


FPGA is not "magic chip that can replace everything".


You will have better chances with fitting the gate array implementation in a CPLD (which is more like EEPROM), if you can find one large enough to fit everything.
Old components are 5V but they speaks each others at 3.3V in fact :D

FPGAmstrad - CPCWiki (http://www.cpcwiki.eu/index.php/FPGAmstrad#Test_of_a_real_Zilog_80) Test of a real Zilog 80
Title: Re: Gate array decapped!
Post by: Bryce on 10:26, 21 September 16
The pre-asic package is quite exotic to today standard. I doubt it's easy to find a socket, and custom ones cost an arm.

Oh yeah, I forgot that. It's one of those rectangular ones isn't it? Not square. Pain in the arse.

Bryce.
Title: Re: Gate array decapped!
Post by: dragon on 14:10, 21 September 16
Oh yeah, I forgot that. It's one of those rectangular ones isn't it? Not square. Pain in the arse.

Bryce.

Is a 30x20 pin. But i unkown the inch of the pads.

Maybe is a qpf(100p6p-e)?.

http://www.ebay.com/p/software-survo-microcomputers-vcr-7770-series-gemstar-m37777m7a253gp-30x20-qfp/1857944337

http://www.glyn.de/data/glyn/media/doc/100s_u.pdf


Adapter to dip : p

http://vi.raptor.ebaydesc.com/ws/eBayISAPI.dll?ViewItemDescV4&item=171251434317&category=36327&pm=1&ds=0&t=1474458097460#&panel1-3
Title: Re: Gate array decapped!
Post by: robcfg on 12:41, 18 October 16
More awesome news from decapping land!


Here you have the metal layer pictures of 40007 gate array (https://mega.nz/#!NgMQgDoL!Yn-4Reta-twO7D1KGC0FDo4syp2cwbWcxHwco64mYq8), 40008 gate array (https://mega.nz/#!01UxgK7B!ueyVlczNcMjYPAr1zYOrlbMyJfzCiKIK3dEBHL2bpzo) and the infamous ACID chip (https://mega.nz/#!Nl0E0JJI!8Sofxqhle-eDN5TIQh3VztZd-_SKo9MNDI7b4qu-QLc).
Title: Re: Gate array decapped!
Post by: Gryzor on 12:48, 18 October 16
Ok, question: who's got a source to make poster prints out of these beauties?
Title: Re: Gate array decapped!
Post by: robcfg on 12:50, 18 October 16
Indeed, they look beautiful.


My favourites are the 40010 and 40008, hehe  :D
Title: Re: Gate array decapped!
Post by: Bryce on 13:14, 18 October 16
Ok, question: who's got a source to make poster prints out of these beauties?

I have a source that can even print these onto banner cloth, so you can hang it as curtains :D

Bryce.
Title: Re: Gate array decapped!
Post by: Gryzor on 13:18, 18 October 16
Eh... I don't think she'd go for it :D
Title: Re: Gate array decapped!
Post by: dragon on 13:24, 18 October 16
Ok, question: who's got a source to make poster prints out of these beauties?


You can make a parasol(i unkown the english word) for car, then all pople can view it :)


Downloading...
Title: Re: Gate array decapped!
Post by: Gryzor on 13:32, 18 October 16
Ah you mean for the windshield, right? That's an idea! :D
Title: Re: Gate array decapped!
Post by: Bryce on 13:40, 18 October 16
I think he means a complete car cover: http://www.5starshine.com/images/coverking/carcoverbigenzo.jpg

Bryce.
Title: Re: Gate array decapped!
Post by: robcfg on 13:51, 18 October 16
Nope, but would be awesome indeed!  ;D


He refers to a windshield shade.
Title: Re: Gate array decapped!
Post by: dragon on 13:57, 18 October 16
Yeah some like these lateral, or frontal, or in the back:

Is very easy find sites do it :

http://www.getsingular.com/parasoles-coche-personalizados.html (http://www.getsingular.com/parasoles-coche-personalizados.html)

[youtube]https://www.youtube.com/watch?v=0VzB_LmGdO4[/youtube]
Title: Re: Gate array decapped!
Post by: dragon on 14:05, 18 October 16
So the 40010-A is the misterius reserved to the finish right? :).
Title: Re: Gate array decapped!
Post by: Bryce on 14:08, 18 October 16
Yeah, but get the Plus ASIC version printed, it has more colours :)

Bryce.
Title: Re: Gate array decapped!
Post by: dragon on 14:26, 18 October 16
One chip per window, the acid in front then you are more protected.

First open 40908 suprise surprise is a thosiba ic. Other gate array new to the family. time to investigate thosiba ics .Maybe the asic manufactuirer is thosiba.

In the 40007 my theory is correct is the ferranti ula 5000R series. If you take in the zx spectrum book the figure 5-24 :R series matrix cells (page  60).

The cells in the ic are exactly equal :)

The 40008 as my theory (yepahhh!!). Is another ferrenti ic chip from 5000r(same model ic?) or maybe 6000r series ula.

Pages 59-70 in zx spectrum book covers 40007 and 4008 strtucture :)
Title: Re: Gate array decapped!
Post by: robcfg on 14:34, 18 October 16
So the 40010-A is the misterius reserved to the finish right? :) .


I have good news for you (https://mega.nz/#!txMRSAJZ!EeVmLFNuLglKwgo5T0T63x0whLQt6ExDQmjXqzdbFxE).  8)
Title: Re: Gate array decapped!
Post by: dragon on 14:54, 18 October 16
You can count the files x cell please , my pentium 4 is so slow with the picture is more bigger that the other?.
Title: Re: Gate array decapped!
Post by: robcfg on 15:53, 18 October 16
I'm astonished!


40010-36AA has 18 rows and 74 coumns (37 pairs), while 40010-37AA has 21 rows and 82 columns (41 pairs)...


Now, I don't know if @gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) will have the time (or the will) to check them for differences.


Another Amstrad fact learnt today  :D
Title: Re: Gate array decapped!
Post by: Bryce on 17:11, 18 October 16
I'm astonished!


40010-36AA has 18 rows and 74 coumns (37 pairs), while 40010-37AA has 21 rows and 82 columns (41 pairs)...


Now, I don't know if @gerald (http://www.cpcwiki.eu/forum/index.php?action=profile;u=250) will have the time (or the will) to check them for differences.


Another Amstrad fact learnt today  :D

That doesn't necessarily mean that they function differently, it may just be a different die with the same mask.

Bryce.
Title: Re: Gate array decapped!
Post by: dragon on 17:23, 18 October 16
That doesn't necessarily mean that they function differently, it may just be a different die with the same mask.

Bryce.

But my theory was right. :) . And now the name in schematics pins compatibility have sense. And is a mystery anyway :)

The model should be in the gate array pdf i put time ago.

The other mistery is the 40007-40008, i think is the same ula. So amstrad made changes to the circuit  to eliminate the heat.

About the acid thosiba makes sense remember the joint  history of thosiba-lsi
Title: Re: Gate array decapped!
Post by: Bryce on 17:32, 18 October 16
Hot spots can occur if lots of fast switching transistors are physically close to each other on the die. To reduce this you spread them around the die by shifting functions from one area to another, but this can force you to re-assign the I/O pins. This can still even happen with modern CPLDs/FPGAs and it's a pain in the arse when you need to do it late in a program. Something like this was probably the reason for the pinout changes.

Bryce.
Title: Re: Gate array decapped!
Post by: 1024MAK on 18:12, 18 October 16
One problem with some ULA chips is that the gate propagation delay changes significantly as the chip temperature increases. This affects the higher speed sections of a design.

That's the problem that Acorn had with the ULA used as the Videoproc in the BBC Micro (hence why a heatsink was fitted to early ULA chips).

In the ZX Spectrum, the vertical lines on the display when inverting, or flashing the character cells is also a propagation delay issue.

Most ULA chips from Ferranti have logic that operates at a lower voltage than the supply. So the chip includes many series regulators around the outside of the logic area. These produce a fair bit of the heat in the chip.

Mark
Title: Re: Gate array decapped!
Post by: gerald on 19:12, 18 October 16
That doesn't necessarily mean that they function differently, it may just be a different die with the same mask.

Bryce.
My bet is just a trade-off between time to market and cost.
37AA version (biggest) done as fast as possible.
36AA version (smallest) is just a re-layout of the same logic on a smaller array to reduce cost once the functionality has been validated.
A quick look show that the overall floor-plan is identical (even the layout of the top-left corner).
The 37AA has far more un-used cells. My bet is that the netlist are identical, but I am not sure I will check it ;)

I may give a shot at 40007/40008 just to understand what has been fixed between the 2 version. The GA used is the same for both (and confirm the 40007/40008 are footprint compatible)
Title: Re: Gate array decapped!
Post by: dragon on 20:04, 18 October 16
Only say the count made by robcfg  21X82=1722 In the pdf=LL3170  Match perfect with the hsg3170 changing the initials to sgs nomenclature.

And of course the other ic count 18x74=1332 in the pdf=LL3130 Hsg3130 with sgs nomenclature.

 :)

Title: Re: Gate array decapped!
Post by: ||C|-|E|| on 22:08, 18 October 16
Aaah... Toshiba, the same brand that made my TV is also the one behind the evil ACID?  :-X
Title: Re: Gate array decapped!
Post by: dragon on 00:35, 20 October 16
My bet is just a trade-off between time to market and cost.
37AA version (biggest) done as fast as possible.
36AA version (smallest) is just a re-layout of the same logic on a smaller array to reduce cost once the functionality has been validated.
A quick look show that the overall floor-plan is identical (even the layout of the top-left corner).
The 37AA has far more un-used cells. My bet is that the netlist are identical, but I am not sure I will check it ;)

I may give a shot at 40007/40008 just to understand what has been fixed between the 2 version. The GA used is the same for both (and confirm the 40007/40008 are footprint compatible)


About year 95 Roland Perry tell this in amstrad group.


"I happen to know that the first chips were Ferranti ULAs made exactly to Amstrad's design, while later models were SGS custom chips which were plug compatible, but not identical at the gate level, allegedly."




I not know what chips they  speak in the part of diferent at gate level.


40008/10 or aa37 aa 36

Title: Re: Gate array decapped!
Post by: RichTW on 13:10, 23 November 16
Hi all!


I just joined up because I've always been fascinated by the unusual video specifications of the CPC and wanted to congratulate all involved in putting together the schematics for the gate array!


I'd always wondered how the hardware palette colour order came to be - I could never determine the logic behind it (even though there appeared to be some order), and was curious about why those particular duplicate colours dropped out of the logic.  So with these schematics, finally it's possible to see exactly how it works, and it's as fascinating and yet as obscure as I might have hoped!  :)   The tristate logic was definitely an unusual feature.


I think I've spotted a small error in the schematic: in the Colour number to RGB decoder, gate U1806 is inverting the wrong input: it should be inverting COLOUR2, not COLOUR0 - this then produces the same results as the hardware colour numbers.


Out of interest, why is there the popular view that originally a 64 colour palette was intended?  Seems to me this would require a really different design - tristate logic would no longer be an option, for a start.  The 27 colour palette seems like a hack which comes from exploiting the tristate outputs without requiring a lot of extra logic to achieve it, compared to a binary (on or off, 8 colour) palette.
Title: Re: Gate array decapped!
Post by: TotO on 14:15, 23 November 16
Out of interest, why is there the popular view that originally a 64 colour palette was intended?  Seems to me this would require a really different design - tristate logic would no longer be an option, for a start.  The 27 colour palette seems like a hack which comes from exploiting the tristate outputs without requiring a lot of extra logic to achieve it, compared to a binary (on or off, 8 colour) palette.
As you said, it look to be a hack to exploit the tristate outputs.
With that, the GA require 3 less pin to display the coulours and the bit5 of the colour register was left unused.
Title: Re: Gate array decapped!
Post by: arnoldemu on 15:00, 23 November 16
Out of interest, why is there the popular view that originally a 64 colour palette was intended? 
There is space in the register for 2 bits for each of r,g and b making 64 colours.

I think that is the only reason this view is held.



Title: Re: Gate array decapped!
Post by: gerald on 18:31, 23 November 16
I think I've spotted a small error in the schematic: in the Colour number to RGB decoder, gate U1806 is inverting the wrong input: it should be inverting COLOUR2, not COLOUR0 - this then produces the same results as the hardware colour numbers.
Well spotted !
That's a miss in the 'simplification' process.
Updated version attached. There is also a fix in the color decode mux (label where missing on output bus).
Title: Re: Gate array decapped!
Post by: PulkoMandy on 11:57, 24 November 16
that 64 colour theory is somewhat coming from my own speculations. What I *think* could have happened is:
- The registers for the gate array were initially designed with 64 colors in mind (2 bit of each red, green, blue) - there is still space for it in the register map, with 1 bit being unused.
- This would have required 6 output pins from the gate array to generate the video signal
- People kept adding features to the chip, and at some point it did use all the 40 pins of the largest package they could get
- They had to free some more pins for other features, and at some point had to settle for video output on just 3 pins
- Fortunately, by using the high impedance trick, this results in 27 colors, instead of just 8, making it a not so bad tradeoff

Of course, I can be wrong and the 27 colors tricks may have been planned from the start. We would have to check with the people who designed the hardware to be sure.
Title: Re: Gate array decapped!
Post by: andycadley on 23:56, 24 November 16
The way I always heard it back in the day is that the original design called for 16 colours, then the designers got clever and spotted the tristate hack could be done pretty much for free and so extended the register design to allow it to work.
Title: Re: Gate array decapped!
Post by: RichTW on 00:01, 25 November 16
That sounds feasible.  I can imagine they might've been going for an RGBI type palette, like the Spectrum, and realised that if they had to have tristate outputs, they may as well find a way to control each one individually instead of all-full or all-half.
Title: Re: Gate array decapped!
Post by: 1024MAK on 14:24, 25 November 16
I suspect that the hardware designers took inspiration from the other existing home micros. You had the ZX Spectrum with 15 colours (7 full intensity "bright" colours, 7 "normal" intensity colours plus black), the BBC model B had 8 colours, the C64 had 16 colours, so the minimum that the CPC should have was 16 colours. But going up to 64 colours may have increased the cost too much (remember the market it was aimed at).

But could they do any better? Well, Sinclair, with their design of ZX81 ULA video circuity had already demonstrated that digital logic could output three voltages instead of just two digital logic levels (low = sync, medium = black signal, high = white level). So presumably someone had a light bulb moment!

The result is the 27 colour system  :D

Mark
Title: Re: Gate array decapped!
Post by: dragon on 15:20, 25 November 16
At the time of cpc release, the majority of enginners was graduate recentlly. Mej electronics was found litte time early.

Its nornal the take a look a other systems as reference.

Anyway at the finish of the day these years. The final especification was conditioned to the space in the ula/cost.

Really, i think if in these days. Amstrad go first with sgs instead of ferranti. We can have a totally diferent especification in the gate array. Sgs apperars have more gates  at same cost.
Title: Re: Gate array decapped!
Post by: Bryce on 15:31, 25 November 16
At the time of cpc release, the majority of enginners was graduate recentlly. Mej electronics was found litte time early.

The university subject "electronics" may have been new, but there were certainly lots of electronics experts that had been around for years, just that their course had been called electrical engineering. Commercial electronics started before the 30's, more than 50 years before the CPC arrived.

Bryce.
Title: Re: Gate array decapped!
Post by: dragon on 12:08, 26 November 16
The university subject "electronics" may have been new, but there were certainly lots of electronics experts that had been around for years, just that their course had been called electrical engineering. Commercial electronics started before the 30's, more than 50 years before the CPC arrived.

Bryce.


Electronics in general yes, but i not speak about it,  i speak about design a home computer. the industry in these time was very new, taking apart the big room industrial computers.


I mean not how build the electronics part, if not the overral design of  how the computer works. how screen is accesed, bus configuration. etc etc.. resolution modes etc..


Mej electronics/amstrad go for the easy part. they take reference of what it exist and take this  reference to desing the computer.

For example video modes are a  a variant of cga.
Title: Re: Gate array decapped!
Post by: robcfg on 02:08, 19 November 17
Hi folks!


I just wanted to say that I uploaded the decapped ACID chip to the wiki page (http://www.cpcwiki.eu/index.php/Amstrad_Cartridge_Identification_Device#Pictures).


Cheers,
Rob
Title: Re: Gate array decapped!
Post by: Gryzor on 10:03, 19 November 17
Oh, you're the one who broke the db with this big beauty :D
Title: Re: Gate array decapped!
Post by: robcfg on 10:13, 19 November 17
Everything’s legal!


The image is under the 20 MB size limit...


 ;D
Title: Re: Gate array decapped!
Post by: Bryce on 09:36, 20 November 17
Looks like a simple gate array.

Bryce.
Title: Re: Gate array decapped!
Post by: Gryzor on 09:37, 20 November 17
What should it look like?

Sent from my HTC 10 using Tapatalk

Title: Re: Gate array decapped!
Post by: Bryce on 09:39, 20 November 17
Well it could have been an ASIC or a custom IC. This is the ACID, not the GA.

Bryce.
Title: Re: Gate array decapped!
Post by: Gryzor on 09:40, 20 November 17
Ah.

Sent from my HTC 10 using Tapatalk

Title: Re: Gate array decapped!
Post by: dragon on 17:37, 18 January 18
So then what is that history about gate array 40010-28710 incompatible with the m4?.

I was thinking that part are a serial number amstrad made gate array subversions?.
Title: Re: Gate array decapped!
Post by: gerald on 17:52, 18 January 18
So then what is that history about gate array 40010-28710 incompatible with the m4?.

I was thinking that part are a serial number amstrad made gate array subversions?.
Where did you get that info ?
If there is an incompatibility issue, I would say M4 is incompatible with 40010-28710, not the other way  ;)
Title: Re: Gate array decapped!
Post by: dragon on 18:03, 18 January 18
Where did you get that info ?
If there is an incompatibility issue, I would say M4 is incompatible with 40010-28710, not the other way  ;)

Lastest posts

https://www.amstrad.es/forum/viewtopic.php?f=36&t=4388&sid=67d37bf02c4f8b5ee4e1ea0f7c4b0dfc&start=315 (https://www.amstrad.es/forum/viewtopic.php?f=36&t=4388&sid=67d37bf02c4f8b5ee4e1ea0f7c4b0dfc&start=315)
Title: Re: Gate array decapped!
Post by: gerald on 18:32, 18 January 18
Lastest posts

https://www.amstrad.es/forum/viewtopic.php?f=36&t=4388&sid=67d37bf02c4f8b5ee4e1ea0f7c4b0dfc&start=315 (https://www.amstrad.es/forum/viewtopic.php?f=36&t=4388&sid=67d37bf02c4f8b5ee4e1ea0f7c4b0dfc&start=315)
interesting. However, swapping the gate array is not a solution.
The M4 is doing/inducing something wrong (likely a timing problem) and this should be fixed. Only a proper analysis with a logic analyser could tell us.
BTW the 28710/28544 are manufacturing date code  ;)
Title: Re: Gate array decapped!
Post by: dragon on 21:04, 18 January 18
Yeah, but if all gate arrays are the same is so strange 28710 fail in three diferent  cpcs. Maybe fault batch?
Title: Re: Gate array decapped!
Post by: robcfg on 21:19, 18 January 18
That particular chip may be partially damaged.
Title: Re: Gate array decapped!
Post by: Duke on 21:55, 18 January 18
I have asked to buy the particular GA, it's still unclear to me if its just one GA with fab code 28710, which makes it less interesting to put time into, as robcfg says, it could have some damage.
If it's really 3, then of course I would like to put it under the LA.
Also I haven't got reply if my beta 9 works with it, which doesn't use the GA signals for timing at all and thus are a significant amount of nano seconds faster asserting romdis and driving the datalines.
Anyway time will tell :)
Title: Re: Gate array decapped!
Post by: gerald on 22:15, 18 January 18
Yeah, but if all gate arrays are the same is so strange 28710 fail in three diferent  cpcs. Maybe fault batch?
Faulty batch ? Why ?
There are obviously some dispersion in IC characteristics, but these are tested to match the manufacturer requirement.
If these have been mounted in a CPC, that mean they passed the qualification test. And the CPC is working fine with them (and without M4)
We need to identify why they fail with the M4.

What I find strange is that one guy have 3 CPC with 3 GA from the same batch  :o :laugh:
Title: Re: Gate array decapped!
Post by: Bryce on 09:28, 19 January 18
The M4 timing is probably too tight and because of that it's not working on chips on the edge of the tolerances.

Bryce.
Title: Re: Gate array decapped!
Post by: jr on 14:11, 14 February 19
Hi all, first I would like to thank for all the information you gathered around the CPC world.
In particular the Gate Array analysis is quite impressing.

After looking into the schematics from gerald and the Verilog implementation from Ash Evans (posted by DaDMaN) I would like to share my findings.
I am not sure, if these topics have been discussed before in another thread, thus I publish them here hoping that the information might be helpful.

Any comments welcome.

Thanks,
jr
Title: Re: Gate array decapped!
Post by: jr on 14:13, 14 February 19
Schematics

I found some things, that do not match my expectations.

Page 2: RESET is an active high signal, i.e. U202 can only be active while RESET is active
    Is this the intended behaviour ?


Page 8:
    U804 is an OR-gate, instead of an AND-gate
    U822 is !HSYNC, i.e. same as output of U801

    My understanding is:
        If PAD_HSYNC is low, U808, U813, U818 and U824 are kept in reset.
        As soon as PAD_HSYNC is high U808, U813, U818 and U824 start counting with CCLK.
        After 4 CCLK clocks, output of U818 is high, which inverts NSYNC via U828.
        After 4 further CCLK clocks, U824 gets high and keeps U808, U813, U818 in reset state.

        This causes the NSYNC output to be active for exactly 4 CCLK clocks starting 4 CCLK clocks after rising edge of PAD_HSYNC.
        Polarity is defined by U806 (high while HCNT<4, i.e. first 4 HSYNC pulses after VSYNC rising edge, low otherwise).


    Comment to U817 function
        U817 is set for one CCLK when HCNT changes from >=4 to <4, e.g. HCNT is reset from 28 to 0
        Assume that HCNT>=4, i.e. U806=0, latched into U812.
        Upon reset of HCNT to 0, U806=1 and U817=1 for one CCLK clock cycle.
        This aligns the interrupt counter to the VSYNC signal, because HCNT changes from 28 to 0 with rising edge of VSYNC (see below).
       
    HCNT counts number of HSYNC rising edges, starting from 0 after VSYNC rising edge
        It stops counting, when HCNT=28 (U802=1).
        Counter is reset by rising edge of VSYNC (U810).


Page 11
    The numbering of CIDX[3:0] should be U1109, U1129, U1119, U1139, i.e. CIDX1 and CIDX2 swapped


Page 13-16 (Colour bit multiplexer)
    U1x04 and U1x17 (x=3..6) are exchanged, i.e. U1x04 negated path should be the "left" wire ("upper" input to U1x05..U1x12) und non-inverted the "right" wire ("lower" input).
    Then CIDX[3:0]=0..15 selects INKRx[0..15].

Title: Re: Gate array decapped!
Post by: jr on 14:21, 14 February 19
Verilog file

a. Resets are missing or are implemented synchronously instead of asynchronously, which is mandatory for proper operation
- U814, U820, U825, U829 (HCNT): U809 is kept in reset, as soon as HCNT[4:2]="111", i.e. no more clocks for the other FF
- U808, U813, U818, U824 (nsync)
- U815, U821, U826, U830, U832, U825 (INTCNT[0:5])
- U708

b. Some copy-paste errors
- U802: HCNT stops counting at HCNT[4:2]="101"
- U1110, U1115, U1120, U1125, U1130, U1135, U1140: Video shift register

c. missing assignments (CIDX)

d. Changes in schematic v0.2
- Verilog file is based on v0.1 and U1806 changed betwen v0.1 and v0.2



Below are the changes I did to the Verilog file, incl. my interpretation of the schematics.
Note, I have (almost) no knowledge about Verilog, but tried my best with help of some online tutorials.
--- "Amstrad CPC 40010 Gate Array implementation in Verilog_pastebin_2019-02-12.v"    2019-02-13 19:47:48.626881209 +0100
+++ "Amstrad CPC 40010 Gate Array implementation in Verilog_only_fixes.v"    2019-02-13 20:14:24.678781786 +0100
@@ -570,7 +570,7 @@
 wire U707 = !M1_N | U705_REG;
 
 reg U708_REG;
-always @(posedge MREQ_N)
+always @(posedge MREQ_N or negedge U707)
     if (!U707) U708_REG <= 1'b0;    // Reset.
     else U708_REG <= 1'b1;            // Else, Clock in a "1".
 
@@ -633,7 +633,7 @@
 wire U831 = U816 | U817 | IRQ_RESET;
 
 wire U801 = !HSYNC;
-wire U804 = U801 & U824_REG;
+wire U804 = U801 | U824_REG;
 
 
 // INTCNT [045] Register...
@@ -645,14 +645,14 @@
 wire INTCNT4_CLK = !INTCNT[3];
 wire INTCNT5_CLK = !INTCNT[4];
 
-always @(posedge U801) if (U831) INTCNT[0] <= 1'b0; else INTCNT[0] <= !INTCNT[0];                 // U815 reg.
-always @(posedge INTCNT1_CLK) if (U831) INTCNT[1] <= 1'b0; else INTCNT[1] <= !INTCNT[1];            // U821 reg.
-always @(posedge INTCNT2_CLK) if (U831) INTCNT[2] <= 1'b0; else INTCNT[2] <= !INTCNT[2];            // U826 reg.
-always @(posedge INTCNT3_CLK) if (U831) INTCNT[3] <= 1'b0; else INTCNT[3] <= !INTCNT[3];            // U830 reg.
-always @(posedge INTCNT4_CLK) if (U831) INTCNT[4] <= 1'b0; else INTCNT[4] <= !INTCNT[4];            // U832 reg.
-always @(posedge INTCNT5_CLK) if (U831 | U827) INTCNT[5] <= 1'b0; else INTCNT[5] <= !INTCNT[5];    // U835 reg.
+always @(posedge U801 or posedge U831) if (U831) INTCNT[0] <= 1'b0; else INTCNT[0] <= !INTCNT[0];                 // U815 reg.
+always @(posedge INTCNT1_CLK or posedge U831) if (U831) INTCNT[1] <= 1'b0; else INTCNT[1] <= !INTCNT[1];            // U821 reg.
+always @(posedge INTCNT2_CLK or posedge U831) if (U831) INTCNT[2] <= 1'b0; else INTCNT[2] <= !INTCNT[2];            // U826 reg.
+always @(posedge INTCNT3_CLK or posedge U831) if (U831) INTCNT[3] <= 1'b0; else INTCNT[3] <= !INTCNT[3];            // U830 reg.
+always @(posedge INTCNT4_CLK or posedge U831) if (U831) INTCNT[4] <= 1'b0; else INTCNT[4] <= !INTCNT[4];            // U832 reg.
+always @(posedge INTCNT5_CLK or posedge U831 or posedge U827) if (U831 | U827) INTCNT[5] <= 1'b0; else INTCNT[5] <= !INTCNT[5];    // U835 reg.
 
-wire U822 = !VSYNC;
+wire U822 = !HSYNC;
 
 
 // HSYNC? Reg...
@@ -665,10 +665,10 @@
 wire U818_CLK = !U813_REG;
 wire U824_CLK = !U818_REG;
 
-always @(posedge CCLK) if (U804) U808_REG <= 1'b0; else U808_REG <= !U808_REG;
-always @(posedge U813_CLK) if (U804) U813_REG <= 1'b0; else U813_REG <= !U813_REG;
-always @(posedge U818_CLK) if (U804) U818_REG <= 1'b0; else U818_REG <= !U818_REG;
-always @(posedge U824_CLK) if (U822) U824_REG <= 1'b0; else U824_REG <= !U824_REG; // !VSYNC (U822) resets this reg.
+always @(posedge CCLK or posedge U804) if (U804) U808_REG <= 1'b0; else U808_REG <= !U808_REG;
+always @(posedge U813_CLK or posedge U804) if (U804) U813_REG <= 1'b0; else U813_REG <= !U813_REG;
+always @(posedge U818_CLK or posedge U804) if (U804) U818_REG <= 1'b0; else U818_REG <= !U818_REG;
+always @(posedge U824_CLK or posedge U822) if (U822) U824_REG <= 1'b0; else U824_REG <= !U824_REG; // !VSYNC (U822) resets this reg.
 
 wire U828 = U806 ^ U818_REG;
 assign NSYNC = U828;    // NSYNC, not "HSYNC". ;)
@@ -677,7 +677,7 @@
 
 
 // HCNT reg...
-wire U802 = HCNT[2] & HCNT[2] & HCNT[4];
+wire U802 = HCNT[2] & HCNT[3] & HCNT[4];
 wire U805 = RESET | U802;
 
 reg U803_REG;
@@ -696,11 +696,11 @@
 wire U825_CLK = !U820_REG;
 wire U829_CLK = !U825_REG;
 
-always @(posedge U801) if (U805) U809_REG <= 1'b0; else U809_REG <= !U809_REG;    // U809_REG
-always @(posedge U814_CLK) if (U810) U814_REG <= 1'b0; else  U814_REG <= !U814_REG;    // U814_REG
-always @(posedge U820_CLK) if (U810) U820_REG <= 1'b0; else  U820_REG <= !U820_REG;    // U820_REG
-always @(posedge U825_CLK) if (U810) U825_REG <= 1'b0; else  U825_REG <= !U825_REG;    // U825_REG
-always @(posedge U829_CLK) if (U810) U829_REG <= 1'b0; else  U829_REG <= !U829_REG;    // U829_REG
+always @(posedge U801 or posedge U805) if (U805) U809_REG <= 1'b0; else U809_REG <= !U809_REG;    // U809_REG
+always @(posedge U814_CLK or posedge U810) if (U810) U814_REG <= 1'b0; else  U814_REG <= !U814_REG;    // U814_REG
+always @(posedge U820_CLK or posedge U810) if (U810) U820_REG <= 1'b0; else  U820_REG <= !U820_REG;    // U820_REG
+always @(posedge U825_CLK or posedge U810) if (U810) U825_REG <= 1'b0; else  U825_REG <= !U825_REG;    // U825_REG
+always @(posedge U829_CLK or posedge U810) if (U810) U829_REG <= 1'b0; else  U829_REG <= !U829_REG;    // U829_REG
 
 
 assign HCNT[4] = U829_REG;
@@ -720,7 +720,7 @@
 wire U836_CLK = !INTCNT[5];
 
 reg U836_REG;
-always @(posedge U836_CLK) if (U834) U836_REG <= 1'b0; else U836_REG <= 1'b1;
+always @(posedge U836_CLK or posedge U834) if (U834) U836_REG <= 1'b0; else U836_REG <= 1'b1;
 
 wire U837 = !U836_REG;
 assign INT_N = U837;
@@ -859,7 +859,7 @@
 // Bit 1...
 wire U1106 = SHIFT & U1104_REG;    // Input from previous bit reg.
 wire U1107 = LOAD & VIDEO[1];
-wire U1110 = KEEP & U1104_REG;
+wire U1110 = KEEP & U1109_REG;
 
 wire U1108 = U1106 | U1107 | U1110;
 
@@ -869,7 +869,7 @@
 // Bit 2...
 wire U1111 = SHIFT & U1109_REG;    // Input from previous bit reg.
 wire U1112 = LOAD & VIDEO[2];
-wire U1115 = KEEP & U1104_REG;
+wire U1115 = KEEP & U1114_REG;
 
 wire U1113 = U1111 | U1112 | U1115;
 
@@ -879,7 +879,7 @@
 // Bit 3...
 wire U1116 = SHIFT & U1114_REG;    // Input from previous bit reg.
 wire U1117 = LOAD & VIDEO[3];
-wire U1120 = KEEP & U1104_REG;
+wire U1120 = KEEP & U1119_REG;
 
 wire U1118 = U1116 | U1117 | U1120;
 
@@ -889,7 +889,7 @@
 // Bit 4...
 wire U1121 = SHIFT & U1119_REG;    // Input from previous bit reg.
 wire U1122 = LOAD & VIDEO[4];
-wire U1125 = KEEP & U1104_REG;
+wire U1125 = KEEP & U1124_REG;
 
 wire U1123 = U1121 | U1122 | U1125;
 
@@ -899,7 +899,7 @@
 // Bit 5...
 wire U1126 = SHIFT & U1124_REG;    // Input from previous bit reg.
 wire U1127 = LOAD & VIDEO[5];
-wire U1130 = KEEP & U1104_REG;
+wire U1130 = KEEP & U1129_REG;
 
 wire U1128 = U1126 | U1127 | U1130;
 
@@ -909,7 +909,7 @@
 // Bit 6...
 wire U1131 = SHIFT & U1129_REG;    // Input from previous bit reg.
 wire U1132 = LOAD & VIDEO[6];
-wire U1135 = KEEP & U1104_REG;
+wire U1135 = KEEP & U1134_REG;
 
 wire U1133 = U1131 | U1132 | U1135;
 
@@ -919,13 +919,14 @@
 // Bit 7...
 wire U1136 = SHIFT & U1134_REG;    // Input from previous bit reg.
 wire U1137 = LOAD & VIDEO[7];
-wire U1140 = KEEP & U1104_REG;
+wire U1140 = KEEP & U1139_REG;
 
 wire U1138 = U1136 | U1137 | U1140;
 
 reg U1139_REG;
 always @(posedge CLK_16M_N) U1139_REG <= U1138;
 
+assign CIDX = { U1109_REG, U1119_REG, U1129_REG, U1139_REG };
 
 endmodule
 
@@ -1057,14 +1058,14 @@
 wire U1317 = !U1303;
 
 
-wire U1305 = (U1301 | INKR[7])  & (INKR[3] | U1304);
-wire U1306 = (U1301 | INKR[15]) & (INKR[11] | U1304);
-wire U1307 = (U1301 | INKR[5])  & (INKR[1] | U1304);
-wire U1308 = (U1301 | INKR[13]) & (INKR[9] | U1304);
-wire U1309 = (U1301 | INKR[6])  & (INKR[2] | U1304);
-wire U1310 = (U1301 | INKR[14]) & (INKR[10] | U1304);
-wire U1311 = (U1301 | INKR[4])  & (INKR[0] | U1304);
-wire U1312 = (U1301 | INKR[12]) & (INKR[8] | U1304);
+wire U1305 = (U1304 | INKR[7])  & (INKR[3] | U1301);
+wire U1306 = (U1304 | INKR[15]) & (INKR[11]| U1301);
+wire U1307 = (U1304 | INKR[5])  & (INKR[1] | U1301);
+wire U1308 = (U1304 | INKR[13]) & (INKR[9] | U1301);
+wire U1309 = (U1304 | INKR[6])  & (INKR[2] | U1301);
+wire U1310 = (U1304 | INKR[14]) & (INKR[10]| U1301);
+wire U1311 = (U1304 | INKR[4])  & (INKR[0] | U1301);
+wire U1312 = (U1304 | INKR[12]) & (INKR[8] | U1301);
 
 
 wire U1313 = (!U1302) ? U1305 : U1306;
@@ -1072,8 +1073,8 @@
 wire U1315 = (!U1302) ? U1309 : U1310;
 wire U1316 = (!U1302) ? U1311 : U1312;
 
-wire U1318 = (U1303 | U1313) & (U1314 | U1317);
-wire U1319 = (U1303 | U1315) & (U1316 | U1317);
+wire U1318 = (U1317 | U1313) & (U1314 | U1303);
+wire U1319 = (U1317 | U1315) & (U1316 | U1303);
 
 wire U1320 = INK_SEL & CIDX[0] & U1318;
 wire U1321 = INK_SEL & CIDX[0] & U1319;
@@ -1117,7 +1118,7 @@
 
 wire U1804 = COLOUR[1] & COLOUR[2];
 wire U1805 = COLOUR[1] | COLOUR[2] | COLOUR[3] | COLOUR[4];
-wire U1806 = COLOUR[2] & !COLOUR[0];
+wire U1806 = !COLOUR[2] & COLOUR[0];
 wire U1811 = U1804 | !U1805;
 wire U1812 = U1806 | COLOUR[1];
 
@@ -1128,14 +1129,14 @@
 wire U1814 = U1808 | COLOUR[3];
 
 
-always @(posedge CLK_16M_N) if (U1809) BLUE_OE_N <= 1'b0; else BLUE_OE_N <= U1810;
-always @(posedge CLK_16M_N) if (U1809) BLUE <= 1'b0; else BLUE <= COLOUR[0];
+always @(posedge CLK_16M_N or posedge U1809) if (U1809) BLUE_OE_N <= 1'b0; else BLUE_OE_N <= U1810;
+always @(posedge CLK_16M_N or posedge U1809) if (U1809) BLUE <= 1'b0; else BLUE <= COLOUR[0];
 
-always @(posedge CLK_16M_N) if (U1809) GREEN_OE_N <= 1'b0; else GREEN_OE_N <= U1811;
-always @(posedge CLK_16M_N) if (U1809) GREEN <= 1'b0; else GREEN <= U1812;
+always @(posedge CLK_16M_N or posedge U1809) if (U1809) GREEN_OE_N <= 1'b0; else GREEN_OE_N <= U1811;
+always @(posedge CLK_16M_N or posedge U1809) if (U1809) GREEN <= 1'b0; else GREEN <= U1812;
 
-always @(posedge CLK_16M_N) if (U1809) RED_OE_N <= 1'b0; else RED_OE_N <= U1813;
-always @(posedge CLK_16M_N) if (U1809) RED <= 1'b0; else RED <= U1814;
+always @(posedge CLK_16M_N or posedge U1809) if (U1809) RED_OE_N <= 1'b0; else RED_OE_N <= U1813;
+always @(posedge CLK_16M_N or posedge U1809) if (U1809) RED <= 1'b0; else RED <= U1814;
 
 
-endmodule
\ No newline at end of file
+endmodule
Title: Re: Gate array decapped!
Post by: Gryzor on 14:22, 14 February 19
Man, that's a deep analysis.
Title: Re: Gate array decapped!
Post by: gerald on 18:14, 14 February 19
Page 2: RESET is an active high signal, i.e. U202 can only be active while RESET is active
    Is this the intended behaviour ?
I don't think so  :D
But that's how it's implemented. I more than triple checked that since it did not looks right.
However, if you test with a real 40010 you'll see that the sequencer does not care about reset.

Page 8:
    U804 is an OR-gate, instead of an AND-gate
    U822 is !HSYNC, i.e. same as output of U801
U804 : I need to check that. [edit] Correct. My note and VHDL confirm, but the schematic is wrong.
U822 : good spot, it's a transcription error when passing from my notes to the schematic. [edit2] well, I already spotted it. My local schematic and VHDL reflect it.

Page 11
    The numbering of CIDX[3:0] should be U1109, U1129, U1119, U1139, i.e. CIDX1 and CIDX2 swapped


Page 13-16 (Colour bit multiplexer)
    U1x04 and U1x17 (x=3..6) are exchanged, i.e. U1x04 negated path should be the "left" wire ("upper" input to U1x05..U1x12) und non-inverted the "right" wire ("lower" input).
    Then CIDX[3:0]=0..15 selects INKRx[0..15].
I've fixed that 2 years ago, but did not publish the updated schematic as I was still validating my VHDL port. And than real life took over  :blank:
I currently have VHDL implementation that works except on some demo, and U804/U822 may be the cause.
I need to find some time to :
- re-compile degate so I can double check that at gate level
- re-install the 40010 PLD test setup
[edit2] BTW, there is missing an inverter on NSYNC ouput on page 8.
Title: Re: Gate array decapped!
Post by: jr on 21:29, 18 February 19
Thanks gerald for the confirmation of my analysis, so far.
The hint with NSYNC will become handy, if I ever should try to connect a monitor to the system.

I have the same problem with real life: It never leaves sufficient time to play around with other stuff.
But it is more important for me ;-)

That's why I will have to pause again for a while with this interesting topic.
To not forget the outcomes of my efforts, I post it here, where it it might of help to others as well.


Seems I found another two issues in the schematics, that you can probably verify easily:

   U304 = (S3 & !S6);   // AND instead of NAND

   CCLK = S2 & S5;   // AND instead of OR


Looking at the schematics, I tried to figure out some aspects of the implementation

Page 1:
   Gate U202 can never become high during operation for two reasons:
      - RESET='0'
      - M1_n, IORQ_n and RD_n will never become active at the same time. Interrupt Acknowledge is M1_n='0' and IORQ_n='0'. RD_n is not active.
   If RESET='1', then M1_n, IORQ_n and RD_n are high impedance, so unsure what happens here.

   Synchronization between S[7:0] to CPU state seems to happen automagically with the wait states inserted by the GA (PAD_READY).
   Note:
      If you use T80 FPGA implementation for the Z80 cpu, you have to align PAD_READY to the rising edge of the T80 clock
      The original Z80 samples WAIT#-signal with the falling clock edge of T2, while T80 samples it half a clock cycle later with the rising edge end of T2.

Page 7:
   The logic around RESET, M1_n, PHI_n, MREQ_n (top input to U710) seems to filter out the MREQ_n used for refresh cycle.
   Note: falling edge of PHI_n is rising edge of Z80, as there is an inverter on the CPC mainboard.
   After M1_n='0' the Z80 always inserts one refresh cycle with MREQ_n='0' (and RFSH_n='0'), which must not be used to assert CAS_n,
   because this could lead to erroneous writes to the RAM.
   Note: RAM is active, if RAS_n='0' and CAS_n='0' and MWE_n=!RD_n when CAS_n='0' during CPU memory access.
   This would result in a memory write to the refresh address, if the refresh MREQ_n-signal would be used, as well.

Another copy-paste error in Verilog file:
   wire U710 = !U708_REG | MREQ_N | !S4 | S5;


jr
Title: Re: Gate array decapped!
Post by: gerald on 22:13, 18 February 19
   U304 = (S3 & !S6);   // AND instead of NAND
Confirmed

   CCLK = S2 & S5;   // AND instead of OR
I beg to differ  ;D It's a NOR.

Page 1:
   Gate U202 can never become high during operation for two reasons:
      - RESET='0'
      - M1_n, IORQ_n and RD_n will never become active at the same time. Interrupt Acknowledge is M1_n='0' and IORQ_n='0'. RD_n is not active.
   If RESET='1', then M1_n, IORQ_n and RD_n are high impedance, so unsure what happens here.

   Synchronization between S[7:0] to CPU state seems to happen automagically with the wait states inserted by the GA (PAD_READY).
   Note:
      If you use T80 FPGA implementation for the Z80 cpu, you have to align PAD_READY to the rising edge of the T80 clock
      The original Z80 samples WAIT#-signal with the falling clock edge of T2, while T80 samples it half a clock cycle later with the rising edge end of T2.
I am wondering if these were not used for chip testing. By applying this pattern, they make sure the sequencer was initialised to a known state.
Using reset only would prevent the other clock generation that the Z80 / CRTC  need.
I've attached the latest version of the schematic.