Right, time for a brief update on this project because ... the boards have arrived!
I have built one (see the snap attached) and generally it's good news, very good news really. There is one glitch but I'll come to that later.
As far as getting the boards done is concerned, I used
Seedstudio for the first time, sending them a set of files generated by the free version of Eagle and picking the standard prototype service with cheap 10-18 day post. I made the order on the 29th April, had an email to say they were in the fab on May 3rd and the boards arrived this week on May 15th. They look pretty good and that timescale is very reasonable considering the price. I will definitely use them again, and indeed I have an opportunity to do so immediately !
So does the board work ? Yes, it does. How well ? Very well, thank you very much and I mean well in the sense that the board works with a voltage supply well under 4V, much lower than the CPLD based prototype, and appears to draw very little current at all. I even have the IDC connector on the right side of the board this time. I have tested on my CPC464 with just the RAM board connected either to a ribbon cable from the edge connector or using one of LambdaMikel's adapters
LambdaMikel's adapters. Tonight I made up another ribbon cable and have tried again with the RAM card connected on the back on my Zaxon DDI-3 board. All fine.
It's all working then, so what's the glitch ?
Well, now there's the thing. Actually to my great disappointment it didn't work first time and I had a bit of debug to do. Obviously I have done the debug to get things working, so that didn't take very long, but I now need to make a couple of changes to the board layout before making boards available for anyone else. I will ship an updated board design to Seeed this weekend, and then based on their turnaround this time I could expect to have boards ready to post out in about 3 weeks time.
If you're interested I can tell you what the issues were.
When the boards didn't work I was a bit stumped. After all, I was confident in the actual logic design since I had prototyped it in the CPLD card and had then simulated the 74 series version to check my mapping. I had even done some basic simulation with timing to be confident that I wouldn't have a timing issue and even if that was a bit imperfect there just seemed to be loads of slack available so a ropey timing issue seemed unlikely too.
If not the logic then most likely the problem was in the layout. How could it happen that the layout would not actually match the original netlist ? This is a bit of a long story, but the gist of it is that I'm using my own Jython/Java code to go directly from a Verilog-like netlist to an Eagle PCB board script in one fell swoop. This works pretty well, for example the CPLD card was right first time, but it does mean that I have to prepare my own component libraries to map from the Eagle libs to a python-based lib format for my own tool. Guess what. I had made an error in the mapping the pin out of 2 of the ICs from Eagle to the python lib: a 7432 quad OR and a 7475 dual latch pair. So, yes I had done the usual checks like write out a netlist from the board design and checked that it matched exactly the original source ... but that doesn't check the internals of the library elements. I should have checked those a little more carefully.
The 7475 error was pretty easy to fix on the board - the enables for the latch pairs were swapped over - and to be fair the 7475 has a pretty weird pin-out for a 74 device anyway. So that was easily corrected and indeed I could fix the remaining boards for that one. Unfortunately the 7432 (mis-)mapping was a bit more complicated. I've resolved that temporarily by just bringing all the socket connections off the RAM board and into a breadboard where I can correct them. I can't see an easy way of fixing this on the board manually. So, a new rev it is then to make a proper job it it, and at these prices it's not exactly a disaster but it will be a little more delay.
I have fixed the library elements and updated my netlister project already. I don't need to change any of the RAM board netlist or component placements so making a new board design is a matter of just rerunning the scripts and then tidying up some of the power trunks and routing manually as I did before. As I say I will probably do that at the weekend and just do a bit more testing of the board in the meantime.
R.
