Author Topic: Sundown 2013  (Read 5121 times)

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Offline ralferoo

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Re: Sundown 2013
« Reply #25 on: 01:25, 17 September 13 »
Is this something you could demonstrate with your FGPA implementation?

Would be nice once it's finished to see a few 'what if' setups :)
Yeah, but it's not a real CPC then... ;)

And I actually run at a 16MHz clock, so I have 13 unused cycles in the cycle of 16! But I was planning to allow them to be used for an optional turbo mode... :D

Offline Sykobee (Briggsy)

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Re: Sundown 2013
« Reply #26 on: 10:51, 17 September 13 »
Actually, the CPC could be tweaked to 3-bit per pixel with relatively simple changes to the gate array, as it enforces a 4-clock cycle on the bus, 2 cycles are used for video RAM, 1 cycle for the Z80 and 1 is wasted.

The simplest solution would be to have 2 extra 8-bit latches and 3 shift registers and then have 3 bytes with 8 pixels in each (so separate R,G,B bytes). The current implementation is done with 1 shift register and some masking.


Well, not RGB bytes but different bits of the palette index. This is more of an interleaved bitplane video memory representation - AAAAAAAABBBBBBBBCCCCCCCCaaaaaaaabbbbbbbbcccccccc...


MODE 1 would be the same but AAAAAAAABBBBBBBBaaaaaaaabbbbbbbb... and I see no reason to not allow a 1 bitplane MODE 1 (and 1,2,3,4 bitplane MODE 0s) as well if that would be possible with few changes.


I expect that would have required a bigger gate array, and thus extra cost, and thus wasn't considered. But that bigger gate array could have allowed for a bigger palette potentially.


It would be interesting to see an FPGA CPC with this mode implemented - but totally incompatible with all software (I guess the firmware can be patched for some compatibility, and MODE 2 stuff should be the same).  Still, as part of a "Turbo-CPC" implementation it could be cool to play around with.

Offline Gryzor

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Re: Sundown 2013
« Reply #27 on: 21:04, 17 September 13 »
Ooh, this is actually pretty!

Offline ralferoo

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Re: Sundown 2013
« Reply #28 on: 10:42, 19 September 13 »
I expect that would have required a bigger gate array, and thus extra cost, and thus wasn't considered. But that bigger gate array could have allowed for a bigger palette potentially.
Yeah, interleaving the bytes requires more space in the gate array for latch/shift registers. The existing implementation is about as simple as you can make it: the register is latched with new video data at 2MHz and the register is shifted left every pixel clock (16MHz for mode 2, 8MHz for mode 1, 4MHz for mode 0). The index to the palette register is formed by reading bits 1,5,3,7 and masking to the size of the palette in that mode.

Interesting, the BBC micro takes the only option to simplify this further - omitting the palette mask, so for mode 2 (or as they call it mode 0), you have to set all the even palette registers to colour 0 and all the odd palette registers to colour 1.

The palette registers are by far the most expensive part of the gate array - 17 8-bit latches takes up quite a lot more silicon than the rest of the video logic in the gate array.

Offline arnoldemu

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Re: Sundown 2013
« Reply #29 on: 11:37, 19 September 13 »
@ralferoo: I am sure your design is close to the original design.
Why 8-bit palette? 5 bits is enough for each, however, it may be more complex to do it this way.

I wonder if we could get the gate-array decapped and scanned like they have done for the visual 6502?
I do have one lying around I could donate.

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Offline MaV

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Re: Sundown 2013
« Reply #30 on: 12:25, 19 September 13 »
The Visual6502 site features a donate site where they encourage people to send in their boards or chips.

visual6502.org HW Donation

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Offline ralferoo

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Re: Sundown 2013
« Reply #31 on: 14:50, 19 September 13 »
@ralferoo: I am sure your design is close to the original design.
Why 8-bit palette? 5 bits is enough for each, however, it may be more complex to do it this way.

I wonder if we could get the gate-array decapped and scanned like they have done for the visual 6502?
I do have one lying around I could donate.
Sorry, my bad. They are 5-bits wide! I was still thinking about the latches needed for video memory! :)