X-MEM, a new memory expansion for all CPC.

[Ast]

@Ast: Please can you post a photo of Roudoudoduodu's asm demo running on your plus with x-mem?

Sorry, i can't. I ´m on holidays during one week. You must wait for my return...

[arnoldemu]

does the asic not assert ramdis when asic ram is active? some ram expansions use diodes, but could they use pullups to handle the two way signal?

[gerald]

does the asic not assert ramdis when asic ram is active? some ram expansions use diodes, but could they use pullups to handle the two way signal?

Ramdis has to be asserted by the extension to prevent access to internal ram.
The asic assert RAMOEn when reading RAM (be it internal base/extension or external)

[Ast]

So to eradicate this bug, you just had to Reset bank by putting #c0 to port #7f before to connect Asic i/o page, am i right ?

[gerald]

So to eradicate this bug, you just had to Reset bank by putting #c0 to port #7f before to connect Asic i/o page, am i right ?

Yes

[arnoldemu]

Ramdis has to be asserted by the extension to prevent access to internal ram.
The asic assert RAMOEn when reading RAM (be it internal base/extension or external)

yes.

ram expansion assert ramdis, but they also listen to ramdis and do not activate if they see it? in this way ram expansion can take priority.

the asic does asset ramdis to block all external and internal ram when asic ram is active?

[gerald]

yes.

ram expansion assert ramdis, but they also listen to ramdis and do not activate if they see it? in this way ram expansion can take priority.

the asic does asset ramdis to block all external and internal ram when asic ram is active?

I don't think any ram expansion listen to ramdis since they have to assert it during an access.
If you look at a 464/6128 schematic, you will see that RAMDIS only disable the buffer that drive the Z80 bus. The ram is read, but the result is just ignored.
On the 6128 PAL, RAMDIS also prevent write to the memory when asserted. This is missing on a 464 and requires some trick for the expansion to work.
RAMDIS is an input with a pulldown resistor. Extension should drive it in a wired or connection (hence the diode).

Basically, if you put multiple ram extension that maps to the same bank, all will be written and all will drive the bus during read. But this is not a problem as data should be the same.

[arnoldemu]

I will need to double check it, but I've implemented this "feature" in arnold wip on the "extraram" branch. it will be merged into the trunk tomorrow.

to test:

fossil update extraram

then build using one of the shell scripts.

if asic ram is enabled it accepts writes. if expansion ram asserts ramdis, then it will be written to. write through will happen.
if expansion ram doesn't assert ramdis, asic assumes internal ram or the 64kb ram it knows about (6128 plus) and no write through will happen.

Implementing this actually cleaned up some code!

[remax]

Strange that problem not exist 6128plus with its 64K expansion. (and no user see it before)
When has occurred? using 128K or more?
If we can find a way to fix the problem I will send a new CPLD for plus users.

And perhaps to CRTC4 users :p (all this remid me of the problems i have my CPC ad the X-Mem).

[Ast]

Crtc 4 users can't have the same problem because you can't access to an eventual asic i/O page 
Asic i/O page doesn't exist on Crtc type 4 ! Cpc Old Gen are not concerned.

[arnoldemu]

To summarize all that has been found by Ast and gerald:

- This problem concerns all ram expansions when used on Plus

- This problem is not isolated to x-mem. All ram expansions will show this problem.

- The problem is seen when extra ram is paged into &4000-&7fff, asic registers are paged into &4000-&7fff and a write is done.

- The problem is not seen with the extra 64KB in the 6128Plus when used without ram expansions. The ASIC knows about it and controls it.

- The problem *is* seen if you connect a ram expansion to the 6128Plus. The expansion occupies c4-c7. The write will go to expansion the read will come from expansion.

- to avoid the problem (choose a ram configuration where expansion ram is not at &4000-&7fff. e.g.

ld bc,&7fc0
out (c),c
ld bc,&7fb8
out (c),c

[TFM]

Well, in the Dobbertin as in the Inicron RAM expansions the Bank &C4-&C7 can be switched on / off. So either CPC or expansion RAM is used.


So what actually is the problem? You bank in some exp. RAM like &CF and MM IO and then?

[Executioner]

ld bc,&7fc0
out (c),c
ld bc,&7fb8
out (c),c

If you're not concerned about what's in lower ROM at the time (eg. if it's not enabled), then you can shorten that to:

ld bc,#7fc0
out (c),c
dec c
out (c),c

[arnoldemu]

Well, in the Dobbertin as in the Inicron RAM expansions the Bank &C4-&C7 can be switched on / off. So either CPC or expansion RAM is used.


So what actually is the problem? You bank in some exp. RAM like &CF and MM IO and then?

It will be a problem for ALL ram expansions and ALL RAM configurations (c4-ff) (ok excluding c0 "mirrors").
So if you page in cc and mm io, a write will still go to ram.

The problem is that you page in expansion ram (any page), you page in mm io and do a memory write. Write goes to mm io AND expansion ram.

Only happens with expansions, asic knows about the extra 64kb 6128. So to test use ANY ram expansion.

[TFM]

Ok, the problem occurs when using expansion RAM between &CC and &FF. (And &C4-&C7 is hit too when using NOT the internal RAM of the 6128 Plus.) A write to MM IO in duplicate writes to the E-RAM. I will verify this with some exotic devices in December (sorry, can't access them before).


Seems that by accident I never felt into this pit when doing stuff for the Plus.

[Ast]

To summarize all that has been found by Ast and gerald:

- This problem concerns all ram expansions when used on Plus

- This problem is not isolated to x-mem. All ram expansions will show this problem.

- The problem is seen when extra ram is paged into &4000-&7fff, asic registers are paged into &4000-&7fff and a write is done.

- The problem is not seen with the extra 64KB in the 6128Plus when used without ram expansions. The ASIC knows about it and controls it.

- The problem *is* seen if you connect a ram expansion to the 6128Plus. The expansion occupies c4-c7. The write will go to expansion the read will come from expansion.

- to avoid the problem (choose a ram configuration where expansion ram is not at &4000-&7fff. e.g.

ld bc,&7fc0
out (c),c
ld bc,&7fb8
out (c),c

@Executioner : Do you think to add this to your new Winape version ?

[Executioner]

@Executioner : Do you think to add this to your new Winape version ?

That may be a bit hard to emulate. If I read correctly, depending on the expansion, the write can go to both the exapnsion memory and ASIC RAM, but what does the read get? Are both the ASIC and expansion driving the bus?

[gerald]

That may be a bit hard to emulate. If I read correctly, depending on the expansion, the write can go to both the exapnsion memory and ASIC RAM, but what does the read get? Are both the ASIC and expansion driving the bus?

A simple (half) way to emulate would be to have the write done on both ASIC ram and extension RAM. That is what happen on the real HW.
A complete emulation is not really possible as both ASIC and extension RAM return a value, the Z80 only seeing the result of the bus conflict.
You can either return garbage, ASIC, RAM or a mix of ASIC/RAM value. But ideally you could trigger some kind of emulator HW exception that will stop the emulator and enter the debugger like a breakpoint.

[arnoldemu]

A simple (half) way to emulate would be to have the write done on both ASIC ram and extension RAM. That is what happen on the real HW.

I have implemented it this way

A complete emulation is not really possible as both ASIC and extension RAM return a value, the Z80 only seeing the result of the bus conflict.
You can either return garbage, ASIC, RAM or a mix of ASIC/RAM value. But ideally you could trigger some kind of emulator HW exception that will stop the emulator and enter the debugger like a breakpoint.

Ok I thought the read would only come from asic registers. I can implement this.

[Ast]

@Arnoldemu : Are you always working on Arnold ? Is window version ready ? Could you give us the link to download it, please ?

[arnoldemu]

@Arnoldemu : Are you always working on Arnold ? Is window version ready ? Could you give us the link to download it, please ?

Yes.
Almost. A release is planned in a few days time.
Yes I will send you a pm.

[gerald]

Ok I thought the read would only come from asic registers. I can implement this.

I need to double check that on HW, looking at the bus with a scope.
However, there is no reason the ASIC do not drive the bus as it is selected, and the RAM extension does not know anything about the ASIC and will drive the bus as well.

[OCT]

Does not work with the XMEM nor my own memory extension.
Are you sure you only use C0-C7 memory banks (1st 64K block of extension RAM) and not others ? Without the XMEM you always reach the 1st 64k extension block, whatever you select.

At least it is not xmem only related, my own interface has the same problem.
@CraigsBar, can you test with your symbiface ?

Which is your own memory extension/interface referred to?

[gerald]

Which is your own memory extension/interface referred to?

Prototype visible here : CPC+ RAM extension ?
Final version had some instability on the compact flash side that need a redesign.
The RAM/ROM is fully functional.

[OCT]

Prototype visible here : CPC+ RAM extension ?
Final version had some instability on the compact flash side that need a redesign.
The RAM/ROM is fully functional.

OIC, great to fill the void until SymbiFace3 Hardwareentwicklung | Dr. Zed's evil Lab
Hardwareentwicklung | Dr. Zed's evil Lab comes to life Really Soon Now, but not "commercialized" in light of TotO's X-MASS & X-MEM (BTW allowing 640kB on 6128s too?) ?

Since mentioned in the testing, does any of these provide an equivalent of the Cherry-T/Khany RAM bank swapper (unless someone has figured out how to replicate that on a CPC6128plus) for the first memory bank, which so often allows to capture 64k code with its defences down? 
an unpublished tip for pyradev users
an unpublished tip for pyradev users
File:Khany's BankSwapper.jpg - CPCWiki
File:Khany's BankSwapper.jpg - CPCWiki