Z80 clock

[kelp7]

Hi,


Just a quick query. Where does the Z80 get its clock from? Is it internal to the chip or is it an external input to the chip? Taking a guess I would say external but just wanted to check. I presume there's some source that does the timing for it.....?

[Bryce]

The CPC has a 16Mhz crystal that produces the main frequency. This is fed to the Gate Array which is clocked at 16Mhz, but it has a divide by 4 circuit and outputs 4Mhz for the system clock. There's a further divide by 4 circuit to create a 1Mhz which is needed for the AY but also used to time the RAM access between the CPU and the CTRC.

Bryce.

[kelp7]

Brilliant, thanks very much for the informative and quick reply. Guess different machines will generate that frequency in different ways, but that definitely answers my question anyway. Thanks again.

[Bryce]

CPUs don't usually have internal clocks, only Microcontrollers tend to have these.

Bryce.

[Apollo]

As I didn't see the info elsewhere, is it right that the CPC+ has a 40MHz clock for the ASIC and 9 divider to 4,44 MHz for the Z80 with additional wait cycles for DMA to even the speed out to a 4,00 MHz equivalent?

[arnoldemu]

EDIT:

"2.10 PAL subcarrier locking The main oscillator for the ASIC is 40MHz. A divide by 9 output at 4.444MHz is provided with a 5:4 mark/space ratio. It is possible to change the main crystal to 9 x 4.33619MHz = 39.902571 MHz, slowing the whole system by 0.25%. This may or may not upset the disk drives, but even if this is the case, a diskless unit could provide PAL subcarrier frequency locked to the master oscillator, thus improving the picture quality. "
The Z80 has the same timings as CPC however, so about 4Mhz, but realistically about 3.3 with wait states.

[Apollo]

Thanks but that info I know already and it just talks about how PAL carrier signal is generated, not in what relation this stand to the Z80.

I remember somebody said to me once at Breakpoint demo party that the Plus Z80 has a 4.44 MHz clock and with the additional wait cycles is a tiny bit slower then the original 4MHz Z80, but I find no information about that relationship either in Wiki, Grimware or any other place I know of. I know very good how the GA and Z80 relate to each other on the normal CPC, but about the Plus there is rather few information available about how the clock signals are generated and how wait states differ to be able to feed the 3 DMA channels.
Sadly I don't have an Oscilloscope here, otherwise I would just open my 6128+ and measure the clock pin and wait pin on the Z80 myself.

It would also make sense to enhance the base clock of the Z80 slightly, to have more wait cycles while HSYNC is active to be able to feed the DMA channels without any bus collisions with the CPU.

So any information or pointers to the right source would be appreciated!

[gerald]

A picture being better than words, I let you count the number of 40MHz cycle that make a 4MHz cycle on the following diagram :
[attach=2]

This is a trace I did of a 6128Plus.

   
• 40MHz signal is taken at oscillator output
• 16MHz signal is taken at CLK16 ASIC output (R168)
• 4MHz is taken at Z80 clock input
• 1MHz is taken at AY clock input
• RAS/CAS/WE/RA/RD taken on RAM devices

Spoiler: ShowHide

As you see, the Z80 is clocked at 4MHz, with a WAIT signals low for 3 cycles out of 4. Like all CPC.

[arnoldemu]

...
other place I know of. I know very good how the GA and Z80 relate to each other on the normal CPC, but about the Plus there is rather few information available about how the clock signals are generated and how wait states differ to be able to feed the 3 DMA channels.

...

It would also make sense to enhance the base clock of the Z80 slightly, to have more wait cycles while HSYNC is active to be able to feed the DMA channels without any bus collisions with the CPU.

The opcodes for the enabled DMA channels are read during HSYNC yes. Execution is processed after that. If you use normal HSYNC width of 6 there is enough time and no collisions. Perhaps if you reduce the hsync width and use DMA there will be but then the picture becomes unstable. If you are splitting the mode multiple times per screen and playing DMA then you will have fun

[gerald]

Thanks but that info I know already and it just talks about how PAL carrier signal is generated, not in what relation this stand to the Z80.

The PAL carrier is not generated by the ASIC, but the ASIC base frequency was chosen to match one of its harmonic to minimise beat frequency.
I do not have a GX4000 with modulator, but it would be interresting to see the effect of a 40MHz oscillator on modulated output.

[Apollo]

@gerald: Thank you very much! That trace is indeed very helpful and at least a wrong imagination I had how the Plus works is now corrected.
Would it not be good to incorporate this trace and info into the wiki? I guess I am not the only one having this kind of questions.

@arnoldemu: So the DMA read cycles from ram are done in the cycles when the GA/ASIC normally reads screen memory, but as this is the HBLANK and no data is read, the otherwise empty wait cycles are used for the DMA ram read? But how is this related to the length of the HSYNC pulse? And by "mode splitting" do you mean the "fake" HSYNC to make the GA reload its mode status in the same line?

[TFM]

Would it not be good to incorporate this trace and info into the wiki?

YES.