CIO Registers (Detailed)

From CPCWiki - THE Amstrad CPC encyclopedia!
Jump to: navigation, search


CIO Registers

  • Control Register 00h - Master Interrupt Control Register (R/W)
 7   MIE    Master Interrupt Enable
 6   DLC    Disable Lower Chain
 5   NV     No Vector
 4   PAVIS  Port A Vector Includes Status
 3   PBVIS  Port B Vector Includes Status
 2   CTVIS  Counter/Timers Vector Includes Status
 1          Right Justifies Addresses
             0=Shift Left (A0 from AD1)
             1=Right Justify (A0 from AD0)
 0          Reset (Caution: If set, requires a 3rd write to resurrect)
  • Control Register 01h - Master Configuration Control Register (R/W)
 7   PBE      Port B Enable
 6   CT1E     Counter/Timer 1 Enable
 5   CT2E     Counter/Timer 2 Enable
 4   PCE/CT3E Port C and Counter/Timer 3 Enable
 3   PLC      Port A-and-B Link Control (0=operate independently, 1=linked)
 2   PAE      Port A Enable
 0-1 LC       Counter/Timer Link Controls (see below)
  • Counter/Timer Link Controls values are:
 0=Counter/Timers are Independent
 1=Counter/Timer 1's /OUTPUT does Gate Counter/Timer 2
 2=Counter/Timer 1's /OUTPUT does Trigger Counter/Timer 2
 3=Counter/Timer 1's /OUTPUT is Counter/Timer 2's Count Input
  • Control Register 20h - Port A Mode Specification Register (R/W)
  • Control Register 28h - Port B Mode Specification Register (R/W)
 7-6  PTS Port Type Select (0=Bit Port, 1=Input, 2=Output, 3=Bidirectional)
 5    ITB Interrupt on Two Bytes
 4    SB  Single Buffered Mode
 3    IMO Interrupt on Match Only
 2-1  PMS Pattern Mode Specification (0=None, 1=AND, 2=OR, 3=OR-Priority)
 0    LTM Latch on Pattern Match (in Bit Mode), or
 0    DTE Deskew Timer Enable (in Handshake Modes)
  • Control Register 21h - Port A Handshake Specification Register (R/W)
  • Control Register 29h - Port B Handshake Specification Register (R/W)
 7-6 HTS Handshake Type (0=Interlocked, 1=Strobed, 2=Pulsed, 3=Three-Wire)
 5-3 RWS Request/Wait (0=Request/WAIT Disabled, 1=Output /WAIT, 3=Input /WAIT,
                       4=Special Req, 5=Input Request, 7=Output Request)
 2-0     Deskew Time (MSBs of Deskew Timer Time Constant, LSB is forced 1)
  • Control Register 08h - Port A Command and Status Register (Parts R/W)
  • Control Register 09h - Port B Command and Status Register (Parts R/W)
  • Control Register 0Ah - Counter/Timer 1 Command and Status (Parts R/W)
  • Control Register 0Bh - Counter/Timer 2 Command and Status (Parts R/W)
  • Control Register 0Ch - Counter/Timer 3 Command and Status (Parts R/W)
 7-5     Set/Clear Command       (Write Only) (see command list)
 7   IUS Interrupt Under Service (Read Only)
 6   IE  Interrupt Enable        (Read Only)
 5   IP  Interrupt Pending       (Read Only)
 4   ERR Interrupt Error         (Read Only)

For Port A/B Registers: 

 3   ORE Output Register Empty   (Read Only)
 2   IRF Input Register Full     (Read Only)
 1   PMF Pattern Match Flag      (Read Only)
 0   IOE Interrupt on Error

For Counter/Timer Registers: 

 3   RCC Read Counter Control    (Read/Set Only - cleared by reading CCR LSB)
 2   GCB Gate Command Bit
 1   TCB Trigger Command Bit     (Write Only) (Read returns 0)
 0   CIP Counter in Progress     (Read Only)

Set/Clear Command List: 

 0=Null Code,  1=Clear IP & IUS
 2=Set IUS,    3=Clear IUS
 4=Set IP,     5=Clear IP
 6=Set IE,     7=Clear IE
  • Control Register 22h - Data Path Polarity Register Port A (R/W)
  • Control Register 2Ah - Data Path Polarity Register Port B (R/W)
  • Control Register 05h - Data Path Polarity Register Port C (4 LSBs only) (R/W)
 7-0 DPP Data Path Polarity bits (0=Non-inverting, 1=Inverting)
  • Control Register 23h - Data Direction Register Port A (R/W)
  • Control Register 2Bh - Data Direction Register Port B (R/W)
  • Control Register 06h - Data Direction Register Port C (4 LSBs only) (R/W)
 7-0 DD  Data Direction bits (0=Output Bit, 1=Input Bit)
  • Control Register 24h - Special I/O Control Register Port A (R/W)
  • Control Register 2Ch - Special I/O Control Register Port B (R/W)
  • Control Register 07h - Special I/O Control Register Port C (4 LSBs only)(R/W)
 7-0 SIO Special Input/Output bits (0=Normal Input or Output,
         1=Output with open drain, or Input with 1's catcher)
  • Control Register 0Dh - Port Data Register Port A (R/W) (directly addressable)
  • Control Register 0Eh - Port Data Register Port B (R/W) (directly addressable)
 7-0     Data Bits7-0 (usually 0=Low, 1=High, unless Polarity is inverted)
  • Control Register 0Fh - Port Data Register Port C (R/W) (directly addressable)
 7-4     Lock Bits3-0 (0=Writing Enabled, 1=Writing Inhibited)(Read returns 1)
 3-0     Data Bits3-0 (usually 0=Low, 1=High, unless Polarity is inverted)
  • Control Register 25h - Port A Pattern Polarity (PP) Register (R/W)
  • Control Register 26h - Port A Pattern Transition (PT) Register (R/W)
  • Control Register 27h - Port A Pattern Mask (PM) Register (R/W)
  • Control Register 2Dh - Port B Pattern Polarity (PP) Register (R/W)
  • Control Register 2Eh - Port B Pattern Transition (PT) Register (R/W)
  • Control Register 2Fh - Port B Pattern Mask (PM) Register (R/W)
 7-0  Pattern Bits (PP/PT/PM for Pattern Polarity/Transition/Mask accordingly)

Possible combinations of the PP/PT/PM Bits are: 

 PM PT PP Pattern Specification
 0  0  x  Bit Masked Off
 0  1  x  Any Transition
 1  0  0  Zero
 1  0  1  One
 1  1  0  One-to-Zero Transition (falling edge)
 1  1  1  Zero-to-One Transition (raising edge)
  • Control Register 1Ch - Counter/Timer 1 Mode Specification (R/W)
  • Control Register 1Dh - Counter/Timer 2 Mode Specification (R/W)
  • Control Register 1Eh - Counter/Timer 3 Mode Specification (R/W)
 7   C/SC Continuous/Single Cycle (0=Singe Cycle, 1=Continuous)
 6   EOE  External Output Enable
 5   ECE  External Count Enable
 4   ETE  External Trigger Enable
 3   EGE  External Gate Enable
 2   REB  Retrigger Enable
 1-0 DCS  Output Duty Cycle Select (0=Pulse,1=OneShot,2=SquareWave,3=Reserved)
  • Control Register 10h - Counter/Timer 1 Current Count Register MSB (R)
  • Control Register 11h - Counter/Timer 1 Current Count Register LSB (R)
  • Control Register 12h - Counter/Timer 2 Current Count Register MSB (R)
  • Control Register 13h - Counter/Timer 2 Current Count Register LSB (R)
  • Control Register 14h - Counter/Timer 3 Current Count Register MSB (R)
  • Control Register 15h - Counter/Timer 3 Current Count Register LSB (R)
 7-0 CCR Current Count Register (Read Only) (8bits of 16bit total)
  • Control Register 16h - Counter/Timer 1 Time Constant Register MSB (R/W)
  • Control Register 17h - Counter/Timer 1 Time Constant Register LSB (R/W)
  • Control Register 18h - Counter/Timer 2 Time Constant Register MSB (R/W)
  • Control Register 19h - Counter/Timer 2 Time Constant Register LSB (R/W)
  • Control Register 1Ah - Counter/Timer 3 Time Constant Register MSB (R/W)
  • Control Register 1Bh - Counter/Timer 3 Time Constant Register LSB (R/W)
 7-0 TCR Time Constant Register (aka Reload value) (8bits of 16bit total)
  • Control Register 02h - Interrupt Vector Register Port A (R/W)
  • Control Register 03h - Interrupt Vector Register Port B (R/W)
  • Control Register 04h - Interrupt Vector Register Counter/Timers (R/W)
 7-0    Interrupt Vector (Bit3-1 may be automatically modified, see below)

Port A/B: In Priority Encoded Vector Mode: 

 3-1    Number of highest Priority Bit with a match

Port A/B: In all other Modes: 

 3-1    Bit3-1=All zero if Error, or otherwise Bit3=ORE, Bit2=IRF, Bit1=PMF

Counter/Timer: 

 3      Not auto-modified
 2-1    Counter/Timer Number (0=C/T3, 1=C/T2, 2=C/T1, 3=Error)
  • Control Register 1Fh - Current Vector Register (R)
 7-0   Interrupt Vector Based on highest priority unmasked IP (IP=int pending)
       If no interrupt pending then all 1's are output (ie. register is FFh)
Retrieved from "https://www.cpcwiki.eu/index.php?title=CIO_Registers_(Detailed)&oldid=65512"