Difference between revisions of "LK Links"
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In the DDI-1, LK1 connects '''both''' to the Expansion Port /EXP pin (which goes to [[8255|PPI]] Port B, Bit5, '''and''' to the AMSDOS ROM bank number selection logic. The latter one allow to map AMSDOS to bank 7 (default), or bank 0. If AMSDOS sees itself mapped to bank 0, then it does automatically load & start the boot sector from drive A (equivalent as when typing |CPM after power-up). | In the DDI-1, LK1 connects '''both''' to the Expansion Port /EXP pin (which goes to [[8255|PPI]] Port B, Bit5, '''and''' to the AMSDOS ROM bank number selection logic. The latter one allow to map AMSDOS to bank 7 (default), or bank 0. If AMSDOS sees itself mapped to bank 0, then it does automatically load & start the boot sector from drive A (equivalent as when typing |CPM after power-up). | ||
| − | == DDI-1:LK2,LK3 - Disc | + | == DDI-1:LK2,LK3 - Disc Write Precomp == |
| − | In DDI-1, LK2-LK3 connect to the Disc Data Separator. | + | In DDI-1, LK2-LK3 connect to the P1/P0 pins of the FDC9229BT Disc Data Separator (P0=LK3, P1=LK2, and fixed: P2=GND). According to FDC9229BT datasheet: ''P2-P0 select the amount of precompensation applied to the write data''. |
== CPC6128:LK7 - Autoboot CP/M == | == CPC6128:LK7 - Autoboot CP/M == | ||
Revision as of 02:51, 20 February 2010
Contents
- 1 LK1,LK2,LK3 - Manufacturer ID
- 2 LK4 - Screen Refresh Rate
- 3 CPC6128:LK5,LK6,LK8 - Disable 128K RAM Banking
- 4 DDI-1:LK1 - Autoboot CP/M
- 5 DDI-1:LK2,LK3 - Disc Write Precomp
- 6 CPC6128:LK7 - Autoboot CP/M
- 7 CPC Plus:LK105 - Autoboot CP/M
- 8 CPC Plus:R128 (10kOhm) - 128K RAM Enable
- 9 CPC Plus:R129 (10kOhm) - Disc Vers Enable
- 10 CPC Plus:R130 (10kOhm) - 8bit Printer Enable
- 11 CPC Plus Cartridges:LK1-LK6 - EPROM Address Lines
LK1,LK2,LK3 - Manufacturer ID
LK1,LK2,LK3 connect to PPI Port B, Bit1-3. The links select the manufacturer name (which is displayed by the BIOS in the power-up message). These LKs exist on all CPC mainboards (in CPC Plus/GX4000 schematics they are named LK101,LK102,LK103).
LK4 - Screen Refresh Rate
LK4 connects to PPI Port B, Bit4. The link tells the BIOS whether it should set-up the CRTC for 50Hz or 60Hz refresh rate.
CPC6128:LK5,LK6,LK8 - Disable 128K RAM Banking
The CPC6128 contains 128K RAM, RAM banking is controlled by a PAL (which assists its Gate Array). However, the 6128 mainboard can be also used for 64K computers - in that case, only 64K would be installed, the PAL would be missing, and LK5,LK6,LK8 would be installed (bypassing the RAM banking logic, and passing signals directly to unbanked RAM). The CPC+ has a similar feature (see R128 below).
DDI-1:LK1 - Autoboot CP/M
In the DDI-1, LK1 connects both to the Expansion Port /EXP pin (which goes to PPI Port B, Bit5, and to the AMSDOS ROM bank number selection logic. The latter one allow to map AMSDOS to bank 7 (default), or bank 0. If AMSDOS sees itself mapped to bank 0, then it does automatically load & start the boot sector from drive A (equivalent as when typing |CPM after power-up).
DDI-1:LK2,LK3 - Disc Write Precomp
In DDI-1, LK2-LK3 connect to the P1/P0 pins of the FDC9229BT Disc Data Separator (P0=LK3, P1=LK2, and fixed: P2=GND). According to FDC9229BT datasheet: P2-P0 select the amount of precompensation applied to the write data.
CPC6128:LK7 - Autoboot CP/M
Same as DDI-1:LK1 (see there).
CPC Plus:LK105 - Autoboot CP/M
Same as DDI-1:LK1 (see there).
CPC Plus:R128 (10kOhm) - 128K RAM Enable
Installed for 128K DRAM, not installed for 64K DRAM.
CPC Plus:R129 (10kOhm) - Disc Vers Enable
Purpose Unknown !!!
- The ASIC (where R129 connects to) should hava nothing to do with the FDC. However, it does control the AMSDOS ROM bank selection: translating ROM bank 7 (or 0) to cartridge bank 3.
- Possibly, removing R129 might disable that feature (so cartridge bank 3 could be only accessed as ROM bank 83h, but not as ROM bank 7, nor 0.
This is not verified, can somebody test what happens when installing/removing R129 ?
CPC Plus:R130 (10kOhm) - 8bit Printer Enable
When installed (default), enables the 8th printer bit, controlled via CRTC. When removed, outputs LOW as 8th bit (as on classic CPCs with 7bit printer port). See also: 8bit Printer Ports.
