Difference between revisions of "V9990"

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(Technical)
(Technical)
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* After reset (including software reset using the control port), all registers are reset to 0. In addition the selected register (port 4) is set to 0 and read and write increment are not inhibited.
 
* After reset (including software reset using the control port), all registers are reset to 0. In addition the selected register (port 4) is set to 0 and read and write increment are not inhibited.
  
* If using software reset and the reset is held, then reading from ports will cause the CPC to hang. I believe it's asserting /WAIT, but I can't confirm.
+
* If using software reset and the reset is held, then reading or writing to the vram data port will cause the CPC to hang. I believe it's asserting /WAIT but I can't confirm.
  
 
* Some registers have additional bits which are not documented. The mask describes which bits are read/write and which are unchanged.
 
* Some registers have additional bits which are not documented. The mask describes which bits are read/write and which are unchanged.
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* In terms of physical addresses, if you consider physical address 0-&3ffff to be VRAM0 and physical address &40000-&7ffff to be VRAM1, then in P1 mode, the physical address equals logical address and in bitmap modes, every even address maps to &0-&3ffff (ever even is VRAM0) and every odd address maps to &40000-&7ffff (VRAM 1). This is described in the PDF.
 
* In terms of physical addresses, if you consider physical address 0-&3ffff to be VRAM0 and physical address &40000-&7ffff to be VRAM1, then in P1 mode, the physical address equals logical address and in bitmap modes, every even address maps to &0-&3ffff (ever even is VRAM0) and every odd address maps to &40000-&7ffff (VRAM 1). This is described in the PDF.
  
* When reading 2bpp and 4bpp data with the POINT command in bitmap modes the pixel is moved into the topmost bits. The value of the remaining bits is unknown at this time.
+
* When reading 2bpp and 4bpp data with the POINT command in bitmap modes the pixel is moved into the topmost bits.  
  
 
e.g.
 
e.g.
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* setting a partial vram write address is ok. e.g. set r0,r1,r2 to &80000, now set r1 to 1. Write will go to 000001. Now set r2 to 2. Write will go to 000201. Now set R3 to 3. Write will go to 030201. There doesn't appear to be a write buffer.
 
* setting a partial vram write address is ok. e.g. set r0,r1,r2 to &80000, now set r1 to 1. Write will go to 000001. Now set r2 to 2. Write will go to 000201. Now set R3 to 3. Write will go to 030201. There doesn't appear to be a write buffer.
  
* v9990 seems to have a 1 byte read buffer. Setting a partial address and the reading vram will return the data from the previous full address set for the first read, but further reads returns correct values. This is only true of r3 and r4. e.g. set r3,r4,r5 to &80000. Now set r3 to 1. First read will come from &000000, second and subsequent reads now come from &000001. Now set r4 to 2. First read comes from &000001, second and subsequent reads come from &000201. Now set r5 to 3. First read comes from &030201, subsequent reads come from &030201.
+
* v9990 seems to have a 1 byte read buffer. Setting a partial address and the reading vram will return the data from the previous address for the first read, but further reads returns correct values. This is only true of r3 and r4. e.g. set r3,r4,r5 to &80000. Now set r3 to 1. First read will come from &000000, second and subsequent reads now come from &000001. Now set r4 to 2. First read comes from &000001, second and subsequent reads come from &000201. Now set r5 to 3. First read comes from &030201, subsequent reads come from &030201.
  
 
[[Category:Hardware]]
 
[[Category:Hardware]]

Revision as of 09:44, 20 October 2018

The V9990 E-VDP-III or 'Graphics 9000' is a Video Display Processor (VDP) by Yamaha which is based on an unreleased VDP (V9978) that was intended for the unreleased MSX3.

This chip is available on graphics cards for the MSX and CPC.

Documentation

Programming Documentation Manual for the V9990 VDP from Yamaha as a PDF.

File:Yamaha v9990.pdf

Technical

The official 'Application Manual' describes the V9990 ports, registers and commands. These additional notes apply to the V9990 used in the CPC Powergraph video board and explain details that are not clearly described or are omitted from the manual.

  • In the following "databus" means that the v9990 doesn't assert the bus, it doesn't provide data, so the value read is "floating-bus" or the value on the z80 databus at the time. More commonly on CPC it's &ff, but there are some configurations of CPC where this differs.
  • Reading from the Kanji ROM ports without a Kanji ROM returns databus values
  • Reading from the write only ports (or unused ports) returns databus values.
  • Palette red data has a mask of &9F (bits red and color key bit), blue and green have a mask of 0x01f.

e.g.

LD BC,&FF64
LD A,14
OUT (C),C
LD BC,&FF63
LD A,0
OUT (C),A

LD BC,&FF61
LD A,&FF ;; <- reading this component back returns &9F
OUT (C),A 
LD A,&FF ;; <- reading this component back returns &1F
OUT (C),A 
LD A,&FF ;; <- reading this component back returns &1F
OUT (C),A 
  • Bits 1,0 of R14 define a ternary counter. If counter is set to 3 then reads will return 0 and writes are ignored. If auto increment is enabled, it will increment as normal. When ternary counter is 2 or 3, then palette index will increment and ternary counter will go to 0.

e.g.

LD BC,&FF64
LD A,14
OUT (C),C
LD BC,&FF63
LD A,3
OUT (C),A

LD BC,&FF61
LD A,&FF 
OUT (C),A ;; write is not done.
LD BC,&FF64
LD A,14
OUT (C),C
LD BC,&FF63
LD A,3
OUT (C),A

LD BC,&FF61
IN A,(C)  ;; read returns last value written to port

e.g.

LD BC,&FF64
LD A,14
OUT (C),C
LD BC,&FF63
LD A,2
OUT (C),A

LD BC,&FF61
LD A,&FF 
OUT (C),A  ;; palette index will be 1, and ternary counter is 0.
  • If a command transfers data, and it requests data to be written to the command data port, then you can't use a read of this port to clear the data request. It must be a write. Similarly, if a command requests data to be read then you can use a write to clear the data request.
  • If you read from a write-only register you will see data-bus value because the V9990 doesn't assert data on the bus.
  • After reset (including software reset using the control port), all registers are reset to 0. In addition the selected register (port 4) is set to 0 and read and write increment are not inhibited.
  • If using software reset and the reset is held, then reading or writing to the vram data port will cause the CPC to hang. I believe it's asserting /WAIT but I can't confirm.
  • Some registers have additional bits which are not documented. The mask describes which bits are read/write and which are unchanged.

Where the mask has a '1' bit, this bit is read/write. Where the mask has a '0' bit this bit remains at 0 and can't be changed.

  - Register 7 (SCREEN MODE): Mask is &FF.
  - Register 9 (INTERRUPT READ/WRITE): Mask is &87
  - Register 15 (BACK DROP COLOR): Mask is &FF 
  - Register 22 (SCROLL CONTROL): Mask is &C1
  - Register 25 (SPRITE PATTERN GENERATOR TABLE BASE ADDRESS): Mask is &CF
  - Register 26 (LCD CONTROL): Mask is &FF
  - Register 27 (PRIORITY CONTROL): Mask is &FF
  • VRAM read/write via registers, 0,1,2 and 3,4,5 and port 0 use *logical* addresses and not physical addresses. Writing in one mode, and then reading back in another can yield different data because the addresses are translated from physical to logical based on the mode.
  • In terms of physical addresses, if you consider physical address 0-&3ffff to be VRAM0 and physical address &40000-&7ffff to be VRAM1, then in P1 mode, the physical address equals logical address and in bitmap modes, every even address maps to &0-&3ffff (ever even is VRAM0) and every odd address maps to &40000-&7ffff (VRAM 1). This is described in the PDF.
  • When reading 2bpp and 4bpp data with the POINT command in bitmap modes the pixel is moved into the topmost bits.

e.g.

if byte in vram is aabbccdd
 
x = 0
aaxxxxx
x = 1
bbxxxxx
x = 2 
ccxxxxx
x = 3
ddxxxxx 

The undefined 'x' appear to be from the upper byte when doing a 16-bit pixel read but more testing needs to be done to confirm this.

  • setting a partial vram write address is ok. e.g. set r0,r1,r2 to &80000, now set r1 to 1. Write will go to 000001. Now set r2 to 2. Write will go to 000201. Now set R3 to 3. Write will go to 030201. There doesn't appear to be a write buffer.
  • v9990 seems to have a 1 byte read buffer. Setting a partial address and the reading vram will return the data from the previous address for the first read, but further reads returns correct values. This is only true of r3 and r4. e.g. set r3,r4,r5 to &80000. Now set r3 to 1. First read will come from &000000, second and subsequent reads now come from &000001. Now set r4 to 2. First read comes from &000001, second and subsequent reads come from &000201. Now set r5 to 3. First read comes from &030201, subsequent reads come from &030201.