How to handle an external 64Kb RAM expansion

[wilco2009]

I'm studing the memory model of the Amstrad CPC to try to design a RAM expansion.


To make it easier I'm trying first to design a model with only 64Kb compatible with the 6128 RAM model.


I think I have more or less clear the model. In CPC 6128 it is managed by the PAL chip IC118.
It handles A14_OUT, A15_OUT, /CAS0  and /CAS1 signals to paging.


Equations for the PAL are deductible easily with the information included in the description of Gate Array Register 3.


Internal memory have diferent configurations depending on the page mode, for instance, in mode 0 Bank3 is located in in the range C000-FFFF, but in mode 3 Bank3 is located in 4000-7FFF.


Taking in account that is not possible to change the configuration of the internal memory from a external device, because IC118 is not included in a CPC464, how is made the paging in the existing 64Kb expansions?


The only way that I can imagine is disabling internal memory with /RAMDIS and to use 128Kb of external memory, but memory expansions like DK'Tronics ones only uses eight 64Kx1 bit chips.


By other hand, in the CPC6128 schematics, /RAMDIS is conected to IC118, but I can't see the use of /RAMDIS in the CPC464 schematics. It is really connected to any place?

[IanS]

Have you read these threads :-
CPC+ RAM extension ?
464 and ram extension ....

Basically the dktronics boards have transistors to pull A15 and MREQ to +5v.