Amstrad Plus and IM2 bug

[arnoldemu]

I tried with incbc.

all yellow.

[Longshot]

@Longshot: all blue.

So each usec of the instruction is concerned.
About "inc bc", the settings are wrong in incbc1.cpr and incbc2.cpr.
---------------------------------------------------------
For the first one :
nop
nop
nop
nop
inc bc
with nbnopinst=2 (for inc bc delay)
---------------------------------------------------------
for the 2nd
nop
nop
nop
inc bc
with nbnopinst=1
---------------------------------------------------------
the nop are dummies nop to fix instruction before the interrupt

[attachimg=1]

(X) NOP is the instruction before the interrupt. the address is on the stack.
When you delete a nop (from the 4), you need to decrease nbnopinst of 1

[dragon]

Hey gerald, you know if the circuit is the same in rev c,d,e with the 74ls127?


They don't have try fix it using m1 right?. I can't folow the tracks.

[arnoldemu]

I am excited to see the results from @gerald and his logic analyzer

[gerald]

I am excited to see the results from @gerald and his logic analyzer

Here you are :
[attachimg=1]
Red marker is at start of IRQ ack which is immediately seen by the ASIC (INTn goes up) : vector is 0x06
Purple marker is at the effective cycle where the Z80 sample the vector, and where the ASIC sees a second acknowledge. Vector is now 0x04.

[arnoldemu]

Red marker is at start of IRQ ack which is immediately seen by the ASIC (INTn goes up) : vector is 0x06
Purple marker is at the effective cycle where the Z80 sample the vector, and where the ASIC sees a second acknowledge. Vector is now 0x04.

awesome.

I guess the second time, the ASIC has already detected the raster int and set bit 7 in DCSR, perhaps also auto-clearing it. Then because the int is still held, it looks at the DMA bits, determines that none are set and defaults to lowest priority DMA.

What happens when A13=1?

[dragon]

Maybe can be fixed gerald?. With minimum invasion from the cpc. For example make  new combinational circuit atached into the z80 you are designing, and desactivated the ic116.


PD arnoldemu at finish you go to try the lk106?.

[gerald]

I guess the second time, the ASIC has already detected the raster int and set bit 7 in DCSR, perhaps also auto-clearing it. Then because the int is still held, it looks at the DMA bits, determines that none are set and defaults to lowest priority DMA.

I think the DMA2 vector is selected just as default one like it happen in most priority encoder.

What happens when A13=1?

DId not capture it for the obvious reasons. The ASIC nIORQ will be identical to the Z80 IORQn.

Maybe can be fixed gerald?. With minimum invasion from the cpc. For example make  new combinational circuit atached into the z80 you are designing, and desactivated the ic116.

Ideally replacing IC116 with a fixed circuit would be possible. Delaying the IORQ from the Z80 by one clock cycle may fix it. However, I just discovered that the version of the GX4000 (MC0123C) I used for the test use a 74LS27 (3 x 3 input NOR) instead of the 74LS02 (4 x 2 input NOR). So it needs already 2 version.
Also, fixing it is nice, but you split the plus user in two : with and without IM2 fix.

[Longshot]

Also, fixing it is nice, but you split the plus user in two : with and without IM2 fix.

I do not understand much in the discussions on electronics...
However, indeed, I am not certain whether it is a good thing "to modify" cpc to correct this bug, because that won't serve any purpose except to make programs that would only work on the modified cpc. Conversely, a program using the bug will not work anymore on a modified cpc.

[roudoudou]

I do not understand much in the discussions on electronics...
However, indeed, I am not certain whether it is a good thing "to modify" cpc to correct this bug, because that won't serve any purpose except to make programs that would only work on the modified cpc. Conversely, a program using the bug will not work anymore on a modified cpc.

Yep, as we know how to avoid the bug, just do it right with the CPC+

As far as i know, there is still no software using IM2 full features so...

...i will prefer softwares 

[arnoldemu]

Maybe can be fixed gerald?. With minimum invasion from the cpc. For example make  new combinational circuit atached into the z80 you are designing, and desactivated the ic116.


PD arnoldemu at finish you go to try the lk106?.

not yet. If I must remove ics, then it is best I do it on a spare plus or gx4000 because I am sure I will break something

If I could do it cutting tracks and joining with wires then yeah I might be able to do that.

[dragon]

I do not understand much in the discussions on electronics...
However, indeed, I am not certain whether it is a good thing "to modify" cpc to correct this bug, because that won't serve any purpose except to make programs that would only work on the modified cpc. Conversely, a program using the bug will not work anymore on a modified cpc.

Thats not same as, i release a 128k game and all 64k users are out.?


Is not the same as, i released a avanced new  cpc board with new features and these new software not work in old hardware?.


So we cancell 128k games, we cancell new toto motherboard, and some new modifciation or expansion  that made new software incompatible with cpc base?

This happend until 1984. Its simply one modification more accesible in the list.


And if he can be done only using the socketet z80
Delaying one cycle without touching the motherboard is perfect.


People modify the cpc case with a dremel, wire the motherboard with wires to make 4mb expansion that have 0 utility and is a crime fix a bug?

[Longshot]

Thats not same as, i release a 128k game and all 64k users are out.?

Amstrad 6128 comes natively with 128k and ram expansion are standard for Amstrad 464/664
Ram expansion do not modify the cpc behaviour.
Modifying the mainboard is not easy for most people (and you lost the guarantee  )

Of course, it's not a crime to fix an hardware bug if it's your pleasure.
You can add 10 gb of ram and 4000 hardware sprites in your cpc, but it's no more a standard cpc.
And so, very few people could admire your augmented cpc...

[dragon]

Of course i know that, thats because i say if can be fixed using z80 sockekt. You don,'t modify the motherboard, put a expansion internally thats all. Gerald is making a bluethoot connection that works in same manner.

I don't like modify cpc to (because probably i kill it lol)'


Gx4000 don't have expansion port anyway




I think amstrad today building was an hotel,maybe sending the warranty, gif you two spare nights  .

not yet. If I must remove ics, then it is best I do it on a spare plus or gx4000 because I am sure I will break something

If I could do it cutting tracks and joining with wires then yeah I might be able to do that.

I generally not cut traks, but i kill one time a acid cause of heat i supose. Best use a bomb unsolder.


I take a look here, if i can found a cheap gx4000  yelow cheap.


@gerald the rare was the 74ls02, in the pictures of wiki a,b use the 74hct02 or the 74ls27n the rest.

[arnoldemu]

Amstrad 6128 comes natively with 128k and ram expansion are standard for Amstrad 464/664
Ram expansion do not modify the cpc behaviour.
Modifying the mainboard is not easy for most people (and you lost the guarantee  )

Of course, it's not a crime to fix an hardware bug if it's your pleasure.
You can add 10 gb of ram and 4000 hardware sprites in your cpc, but it's no more a standard cpc.
And so, very few people could admire your augmented cpc...

I would advise you to not look at the thread about the msx graphics card on the cpc. 

[arnoldemu]

@gerald : Please can I put the picture from your logic analyzer on the wiki please?
I want to update the wiki.

[gerald]

@gerald : Please can I put the picture from your logic analyzer on the wiki please?
I want to update the wiki.

Done : http://www.cpcwiki.eu/index.php/File:IM2_Plus_Ack_Bug.png
I would suggest to have a separate page if possible. The IM2 bug seems to be a side effect of a fix for an other bug 

[arnoldemu]

Done : http://www.cpcwiki.eu/index.php/File:IM2_Plus_Ack_Bug.png
I would suggest to have a separate page if possible. The IM2 bug seems to be a side effect of a fix for an other bug 

Done.

I hope I explained it well enough for both technical and non technical to understand.

http://www.cpcwiki.eu/index.php/Plus_Vectored_Interrupt_Bug

[Longshot]

Done.

I hope I explained it well enough for both technical and non technical to understand.

http://www.cpcwiki.eu/index.php/Plus_Vectored_Interrupt_Bug

Little mistakes :
Missing "occurs" :
"The bug also doesn't xxxx with opcodes that don't use memory read/write..."
Have you tried with the inc bc at the right place ?
The last test with incbc was wrong because int trigger in "nop" and not in "inc bc".

"Bits 3..1 are generated by the ASIC based on the interrupt source (one of the DMA channels or raster interrupt). Bits 7..4 are defined "
You mean "Bits 2..1" and "Bit 3..7" 

[arnoldemu]

Little mistakes :
Missing "occurs" :
"The bug also doesn't xxxx with opcodes that don't use memory read/write..."
Have you tried with the inc bc at the right place ?
The last test with incbc was wrong because int trigger in "nop" and not in "inc bc".

"Bits 3..1 are generated by the ASIC based on the interrupt source (one of the DMA channels or raster interrupt). Bits 7..4 are defined "
You mean "Bits 2..1" and "Bit 3..7" 

thankyou. I have updated it.

yellow for inc bc. I hope I got it right.

[gerald]

Done.

I hope I explained it well enough for both technical and non technical to understand.

http://www.cpcwiki.eu/index.php/Plus_Vectored_Interrupt_Bug

In fact the bug can happen for any of the vectored IRQ and not only the raster one.

[arnoldemu]

In fact the bug can happen for any of the vectored IRQ and not only the raster one.

I guess the auto-clear (IVR bit 0=0) must be used on the DMA channels to see this?

It needs another test I think to see it happening

[andycadley]

Done.

I hope I explained it well enough for both technical and non technical to understand.

http://www.cpcwiki.eu/index.php/Plus_Vectored_Interrupt_Bug

Seems reasonably clear, nice to see we have got to the bottom of this (although it's curious what the purpose of the added circuitry was), I have to admit to getting lost once logic analysers got involved! I'll have to have a play and make sure I'm clear what the implications are. Am I right in thinking it means that it matters where the interrupted code is, but not the data that it is accessing? That would certainly seem to make avoiding it feasible in some circumstances (presumably not using auto-clear and manually checking on a DMA0 interrupt that it isn't really meant to be a raster interrupt would also work?)

[dragon]

Nobody have the rev a board of the plus.?


Appears amstrad not respect the service manual.



The 464+ b ic116 is diffetent connection that service manual.


Andycalley read choronograme is easy.


The are two states 0 and 1 0 is low so is with the line down.


1 is up so the line is up. The vertical lines is the time is switching between 0 and 1( that in the circuit is change 0v to 5 increasing decreasing voltage.


You view the lines of the ic and z80. So yo are reading  what happend in all pins. At same time in diferent moments.


Then you only need know, if the pin is activated in low(0) or high(1)


For example Iorq is active low, reset low, and a13 is low. 0 0 0 so the line is down at same time and niorq is up, because the ic 116 changue it from 0 to 1. As is active low, asic thing is not activated how a light with a switch.


I mean more easy, imagine the asic is  a light and the ic 116 is a switch.


Normally if the switch was the z80 it turn the light on to interrupt you, when it ends it turn off the light.


If the switch is the ic 116 it works in same manner. Except if you are not alone. Then it turn out the light, interrupt you, switch off the light. And few moments later switch on the light. Then interrupt you two times. And bug happend two interuptions two responses, first good, two bad.


I expect made a good explanation

[arnoldemu]

...Am I right in thinking it means that it matters where the interrupted code is, but not the data that it is accessing? That would certainly seem to make avoiding it feasible in some circumstances (presumably not using auto-clear and manually checking on a DMA0 interrupt that it isn't really meant to be a raster interrupt would also work?)

yes to both.