CPC+ RAM extension ?

Started by gerald, 22:48, 09 October 12

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gerald

Some question I have on + range.
Was there some commercially available 464+/6128+ RAM extension ?
Is there any DIY one?

Now, why this question ?
I am currently testing my own RAM/FLASH/CF extension. All seems fine on 6128, but am facing some issue when connected to the 6128+.

Visible symptoms are display corruption and random crash when reading the extension RAM. Writing phase is OK.

After some test, I've probed the DRAM within the plus and found that when probing the RAM RAS signal, the problem vanish.
Also DRAM timing diagram when reading/writing to the extension looks  weird as the RAS is going high at the same time the CAS is going low, like the access has been masked, but not completely. I was expecting that CAS did not go low at all.

Is anyone aware of potential RAM timing issue on the + range ?

TFM

The only thing I can tell is that all commercial RAM expansions (and that one from Inicron) do work with both the CPC6128 and the 6128Plus. So it shall be doable.
However I do also know that there are some issues with the SYMBiFACE II when running on the Plus. Dr. Zed may know more about it.
TFM of FutureSoft
Also visit the CPC and Plus users favorite OS: FutureOS - The Revolution on CPC6128 and 6128Plus

MacDeath

#2
Concerning the 464PLUS, the most obvious way is to simply put the missing components ont the motherboard so you have a real 4128PLUS.


On the other hand those computers could have some RAM sticks socket, a bit like the Atari STE... but Amstrad didn't care.


Some issues with RAM extensions and 6128 configs, is that the already existing +64k are often simply replaced by the external +64K... so you may have no gain at all actually.


You should perhaps check up the connections too... are you sure the RAM you put on the extension port is well connected and well powered ?
Also are the RAM chip really compatible ?

gerald

I did check the DRAM timing on the CP6128 and found that the RAS/CAS timing where more as expected.

Basically, when accessing the external ram (RAMDIS high), the access to the DRAM is masked.
Masking is done on the CAS cycle of the access, the RAS cycle is still done. However, this masking is only partial and CAS will pulse at the end of the access.

On the 6128, the CAS is going low about 14ns after RAS is going up. That is CAS pulse is not seen by the DRAM as expected with RAS high;
On the 6128+, the CAS is going low about 4ns after RAS is going up. It seems that the DRAM is sometimes taking that for a proper access and memory corruption occur.

As hinted by the fact that problem disappeared when probing the signals, I added 12pf capacitor on both CAS signal.

Now the 6128+ is stable with and without the ram extension.


TFM

So, you added the capacitor the the Plus PCB?

It would be interesting to see if this capacitor also solves the problems which has the sf2 with the Plus.
May you like to post a picture ...

How big is your RAM expansion?
TFM of FutureSoft
Also visit the CPC and Plus users favorite OS: FutureOS - The Revolution on CPC6128 and 6128Plus

gerald

Quote from: TFM/FS on 18:14, 10 October 12
So, you added the capacitor the the Plus PCB?
Yes. The capacitors are between NCAS0/NCAS1 and GND, on the DRAM side. I've soldered them directly on the R155/R156, but these can be soldered on the DRAM pad as well. Basically the increased capacitive load creates a small delay.

Quote from: TFM/FS on 18:14, 10 October 12
It would be interesting to see if this capacitor also solves the problems which has the sf2 with the Plus.
I would be interrested too. Does anyone have the sf2 and a plus with problem ?

Quote from: TFM/FS on 18:14, 10 October 12
How big is your RAM expansion?
512KByte "only"  :P

arnoldemu

Does the ram expansion handle the c3 configuration?
If so how did you implement it?
My games. My Games
My website with coding examples: Unofficial Amstrad WWW Resource

gerald

Quote from: arnoldemu on 19:35, 10 October 12
Does the ram expansion handle the c3 configuration?
If so how did you implement it?

Yes, C3 is part of the specification.
I currently did not test it specifically, but since FutureOS running fine,  I guess that it is OK  :) .
I will make more exhaustive test later. I am only fully testing mode C4 to C7.
From the extension point of view, C3 is not different from C1. The tricky part is done by the PLD inside the CPC when mapping the upper base 16K to 0x4000.
That is, C3 will not work on 464/664.

Kris

Any pictures of this modification ? It may help some of us to fix this issue on Plus ;)
Thanks

gerald

Here it is

Cap value is 12pf, 0603 package. The value is arbitrary and is the 1st one I tested.
You may use any other package.
Let us know if this is working for you.


00WReX

Any pictures of your expansion, and once it's all sorted are you going to release details or maybe build & sell some ?

cheers,
Shane
The CPC in Australia...
Awa - CPCWiki

IanS

Quote from: gerald on 19:48, 10 October 12
That is, C3 will not work on 464/664.
Yet dk'tronics managed to make it work Memory Expansion - Code 3


Do you have any idea how they could have done it?

gerald

Picture of the prototype
[attachimg=1]

Quote from: 00WReX on 14:26, 11 October 12
and once it's all sorted are you going to release details or maybe build & sell some ?

Well, as you said, all need to be sorted out.
Current status is :
  512K RAM is OK in C4-C7 mode, C3 seem OK, did not test C1/C2.
  512K FLASH is OK. However, slot 0 and 7 cannot be used (disabled by default in HW). Flash is programmed using a modified version of TFM ROM manager (Thanks for sharing the code !!! )
  CF raw access are OK, however I have some stability issue I need to solve. Hopefully these are related to the prototype nature and long wires.
  Read only support for FAT12/16/32 including directory and long name. No AMSDOS integration yet

What I still need to do :
  Properly check C1/C2/C3 RAM mode
  Ability to remap 1s 64K of the extension to a new location, so 6128 2nd bank is still used and CPC can access the full 640K. I plan to use the additional 64K for file system cache.
  Ability to remap FLASH slot 31 to low ROM.
  Add I2C RTC, a nice to have for mass storage.
  Add write support to FAT filesystem.
  integrate FAT support in AMSDOS.

I will then at least release the details of the interface (schematic/code). Building and selling is an other story I will think of later  :P
 

gerald

Quote from: IanS on 15:02, 11 October 12
Yet dk'tronics managed to make it work Memory Expansion - Code 3


Do you have any idea how they could have done it?
No Idea at all  ;D . I do not have dk'tronics memory extention to test.
I will try some test later, but for this I need to get my 464 out. The 6128 and 6128+ already take some space.

IanS

Quote from: gerald on 16:38, 11 October 12
  512K FLASH is OK. However, slot 0 and 7 cannot be used (disabled by default in HW). Flash is programmed using a modified version of TFM ROM manager (Thanks for sharing the code !!! )
Looks good. I did the same in my Flash rom, just mapped out 0 and 7.


How are you enabling write support, there doesn't appear to be any obvious switches. Are you using software write control?

TotO

Quote from: gerald on 16:38, 11 October 12512K FLASH is OK. However, slot 0 and 7 cannot be used (disabled by default in HW). [...]  Ability to remap FLASH slot 31 to low ROM.
If the ROM 0 can't be used, why not remaping it for the Lower ROM ? (instead of losing the ROM 31)
"You make one mistake in your life and the internet will never let you live it down" (Keith Goodyer)

Bryce

He's probably enabling the write pin using the address bit of some other ROMs higher up the table: ie: writing to ROM63 is essentially writing to ROM31 etc. I considered this on the MegaFlash, but in the end I chose to use a physical switch to be 100% sure that other hardware wasn't inadvertantly setting the write enable.

@Gerald: Nice hardware, it'll be an impressive little device when it's finished.

Bryce.

gerald

#17
Quote from: IanS on 17:59, 11 October 12
How are you enabling write support, there doesn't appear to be any obvious switches. Are you using software write control?

Yes, write is SW controlled by selecting ROM using port DExx instead of DFxx.
There will be switches to individually enable high rom0, rom7, lower rom0 and globally disable all ROM.

Edit : DExx instead of DFxx is inspired by Yarek internal flash

TFM

Quote from: gerald on 16:38, 11 October 12
Flash is programmed using a modified version of TFM ROM manager (Thanks for sharing the code !!! )

My pleasure. :) Let me know if I can help in any way with ROManager  :)
TFM of FutureSoft
Also visit the CPC and Plus users favorite OS: FutureOS - The Revolution on CPC6128 and 6128Plus

gerald

Quote from: Bryce on 18:07, 11 October 12
I considered this on the MegaFlash, but in the end I chose to use a physical switch to be 100% sure that other hardware wasn't inadvertantly setting the write enable.
I've considered a write switch as well, but :
   - I've tried to minimise the number of switches and reseve them for functional option (like specific rom enable)
   - the flash used is programmed using the standard JEDEC algorithm (simple FSM, but unlikely to do unlock it by accident). so even if the SW unlock the write, the CPC may crash by read the ROM, but the flash should not be corrupted. The flash used on the MegaFlash uses a really simple algorithm, but is easy to corrupt by accident if not write protected.

Quote from: Bryce on 18:07, 11 October 12
@Gerald: Nice hardware, it'll be an impressive little device when it's finished.
Thanks  ;)

gerald

Quote from: TotO on 18:05, 11 October 12
If the ROM 0 can't be used, why not remaping it for the Lower ROM ? (instead of losing the ROM 31)

ROM and ROM7 will be usable later. Current PLD just disable them.

The Idea is to be able to have :
  Internal  Low ROM replaced external high ROM31. When in this configuration, higher ROM31 is no more visible
  Internal High ROM0 replaced external high ROM0
  Internal High ROM7 replaced external high ROM7
All at the same time, so TFM will be able to give us a FutureBasic  :D .


TFM

Quote from: gerald on 18:59, 11 October 12
The flash used on the MegaFlash ... is easy to corrupt by accident if not write protected.

Therefore I do recommend to enable the SDP after installing all ROMs. With SDP active it's nearly impossible that the Flash gets corrupted.
The last update of ROManager supports to enable / disable the SDP, this feature was missing in the first release of the application though.
TFM of FutureSoft
Also visit the CPC and Plus users favorite OS: FutureOS - The Revolution on CPC6128 and 6128Plus

gerald

I would be even better if the Rom manager does the lock/unlock sequence automatically when programming/erasing a rom slot.

TFM

Quote from: gerald on 19:09, 11 October 12
I would be even better if the Rom manager does the lock/unlock sequence automatically when programming/erasing a rom slot.

Well, I actually thought about that... but in that case it would make the Flash in-accessible for other software like QCMD. And in France they do a remake of the MF, using a ROM which provides a simple !BURN command for people who like it easy (which don't know about SDP either).

Well, but back to topic! I'm really curious what your card will be able to do at the end. I like the idea of the mass-storage option. If it would have a mouse port and an RTC then it would be the new SF2  ;D
TFM of FutureSoft
Also visit the CPC and Plus users favorite OS: FutureOS - The Revolution on CPC6128 and 6128Plus

gerald

Quote from: TFM/FS on 19:13, 11 October 12
Well, I actually thought about that... but in that case it would make the Flash in-accessible for other software like QCMD. And in France they do a remake of the MF, using a ROM which provides a simple !BURN command for people who like it easy (which don't know about SDP either).
Nothing killing, just add the lock/unclok to the ROM and QCMD  ::) . It would be safer for everyone and save some time when using a brand new flash.

Quote from: TFM/FS on 19:13, 11 October 12
Well, but back to topic! I'm really curious what your card will be able to do at the end. I like the idea of the mass-storage option. If it would have a mouse port and an RTC then it would be the new SF2  ;D
RTC is planned  :laugh:
But no mouse, as Bryce adapter solution seem more compatible than the SF2 one.

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