CPC / Raspberry Pi Bridge Card

[SerErris]

Although i have access to 32 gpio ports 4 are on this ugly flat camera connector plastic ribbon type thing... 3 i can forego but 1 i cannot which is ramdis. 


Are there ICs that eg... block a signal in a direction so i can connect ramdis that is output and and the rd signal that is always input to the same gpio? So that when the gpio is in it reads rd... but if it is out it write to ramdis? Ramdis needs to be kept high on out... so is such an ic a latch?

First of all you need compareable signals. So it needs to be either both control (with same logic) or both data.
So you could potentially pair read and write. This can be done similar what UPDI does.

UPDI is a serial protocol that uses a single line for read and write. It uses a diode and a resistor to separate read from write traffic. However you need to ensure (protocol level) that read and write never can occure concurrently. But that is true for the CPU anyhow.

https://github.com/SpenceKonde/AVR-Guidance/blob/master/UPDI/jtag2updi.md

Another way would be to use the ~WR line, a tri-state buffer and an OR gate.

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If ~WR is high, the tristate will enable the signal from ~RD to get to your GPIO PIN, The signal from ~RAMDIS will never get to the PI. Also if ~WR is high One of the input of the OR gate is high, resulting in ~RAMDIS high, regardless of what happens to the other input (actually the Output from the tristate buffer.

If ~WR is low the tristate is going to high impedance (actually floating) and whatever is on the GPIO PIN is getting to the OR gate. The OR gate however is having one pin tied to low, so the output is just reflecting what the other input is doing. 

So ~WR acts like an enablement for whatever the other line is doing. 

However, this does not preserve any state. So for instance you cannot set RAMDIS and then try to read anything. Because as soon as you activate the tristate, ~RAMDIS will become high and RAM is enabled again.

I am not sure if that is matching your question, but that is normally how you solve those issues. 

If you need state, you need to put a FlipFlop to the position of the OR gate. The flipflop can be activated on low clock (e.g. still the ~WR signal) and then outputs whatever you have written to it until you change it again.

[zhulien]

i will have to read that again but thanks for the reply.  I understand the concurrent nature - so even if i could use it for both input and output, it wouldn't be at the same time exactly - i will need to have a think abou tthat.

[SerErris]

I made a mistake in the above diagram.

RAMDIS is actually active high. The reason for that is, that the RAM (as well as ROM) has an ~OE signal that activates the RAM/ROM with active low.

For the ROM ~OE is directly connected to a pulldown resistor (so it is always low if nothing else drives it) and for RAM it is going through an OR gate. One half is coming from the GA and the other part is coming from the RAMDIS signale from the expansion port.

In the schematic below you can see how ROMDIS works with the internal ROM chip. Normally the Output Enable (~OE) it is enabled via the pulldown Resistor R112 as it is an active low signal. Then the GateArray defines if it be active with the chip select (~CS) signal and only if both are low, the ROM actually outputs data to the Bus. 
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If an external ROM is getting selected it actually drives ROMDIS high, which subsequently disables the output of the rom. 

It works similar with the internal RAM. However as the RAM does need to be enabled all the time for the video display, here it is separated from the CPU via a latch (IC114). And the output enable (~OE) line is also connected to the Gatearray and the RAMDIS line from the expansion port. That is an OR gate (IC112) that works the same way as in the diagram I posted above.

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One input is connected to RAMDIS of the expansion port and is also pulled down via R124 to low. The other signal is coming from the GateArray.
If nothing is connected to the expansion port this OR gate has one line always 0, so the output will represent directly what the GateArray outputs on ~RAMRD signal. 

If you have an external RAM card (and do not have any other logic in it), the card can pull up RAMDIS, so the data from the internal RAM will never reach the CPU, instead any read will go to your external RAM card and writes will go to both.