cpc+ timings

Started by arnoldemu, 14:05, 03 March 10

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arnoldemu

I was thinking about this the other day.

We know that on the CPC, wait states are added for every memory access.

So it made me think, is this true for CPC+ too?

Are wait states added if you read from cartridge ROM?
Are wait states added if you write to ASIC registers?

I was thinking that if you had some code in the cartridge, it would be possible to copy data from the cartridge rom into the asic registers, and if there was no wait states, then you could write data faster than if you had the code in the main ram. The idea then is that writing code for cartridges ends up with faster execution than standard ram, giving another advantage to cpc+...

When paging in the ASIC ram you can choose which of the first 8 cartridge pages are active in &0000-&3fff, so having both active at the same time you theoretically could copy stuff between the two faster if there were no wait states.

Is there anyone who could test this?

Are the wait states active for reading carts and writing to asic ram?
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PulkoMandy

Of course there are still wait states.
What happens is the Gate Array ask to take control of the memory bus. The memory bus is shared by all devices, unlike the amiga. On the amiga they separated the bus in two parts, fast and chip ram, but on the CPC, they didn't. Everything is on the same bus and the gate array always generate the wait state.
This is needed so the Gate Array can get the bus to read the video ram... on the plus it is also used to read the DMA data (during the HBL).

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