CPC TURBO First Level - project

[Bread80]

That's ridiculously slow logic!

The Motorola datasheet on BitSavers has nicer timings, especially for later revisions https://bitsavers.trailing-edge.com/components/motorola/_dataSheets/6845.pdf

Using an RC network for such delays leaves me feeling queasy. I'd prefer to see a couple(?) of latches trigger by a clock edge. Eg with a 74xx74:
Clock to CLK (inverted if need to be to the correct edge)
/IORQ to D
inverted /IORQ to the /SET input

I'm not sure how you're generating /WAIT but I'd use a similar strategy there (to lengthen the /IORQ pulse as needed).

And I'd probably to that for all I/O to OG devices as they'll all be pretty slow compared to a 20MHz CPU.

[McArti0]

Using an RC network for such delays leaves me feeling queasy. 

This is just delay marking for simulation purposes.  
Basing a precision delay on 10pF would be fun   This is basically the capacitance of a protection diode on the TTL input.
In the link to the emulation I wrote that it is a concept.

The circuit is based on the counters in the SLG46826v-DIP.

Yesterday ROM and CRTC worked but RAM or NewPAL and GA were not set.

I thought I would be able to run it without using an oscilloscope like in the 90s, but I found that I was already being doped by the figs on your website.

I bought two cheap zt-703s and dpox180h. I'll check if they are suitable for such applications.

[McArti0]

I'm not sure how you're generating /WAIT but I'd use a similar strategy there (to lengthen the /IORQ pulse as needed).

In this version WAIT is original from GA. IORQ I have 20ns extended by propagation on gates, but shortened by high clock tick no. 3 and 4.

[McArti0]

I'd really like to be able to add extra GA registers. The current scheme is a little ... cramped.

Out &7fff,'B' and &3F
Out &7fff,'r' and &3F
Out &7fff,'e' and &3F
Out &7fff,'a' and &3F
Out &7fff,'d' and &3F
Out &7fff,'8' and &3F
Out &7fff,'0' and &3F

Out &7fff, R0-63
Out &7fff, nn
A=Inp(&7fff)

[McArti0]

First version Turbo CPC Half Level is working. 

Benchmark v1.0 - 575 to 515 (+11%)

[McArti0]

Benchmark v1.0 559/515=8,5%

BUT IORQ is unchanged.

FDD 765 works perfectly.

SymbOS 4.0b works perfectly.

@Prodatron write benchmark. 

[McArti0]

Benchmark v1.0 574/515=11,4%

Benchmark v1.1 67/58=15,5%

Code Select Expand

1 DEFINT L:AFTER 50 GOSUB 5
2 L=L+1:x=SIN(45):GOTO 2
5 PRINT L
ps. CP/M Plus works well.

[Prodatron]

Benchmark v1.0 559/515=8,5%

BUT IORQ is unchanged.

FDD 765 works perfectly.

SymbOS 4.0b works perfectly.

@Prodatron write benchmark. 

Is that really true? So you are going to make it? That sounds fantastic!

[McArti0]

So you are going to make it?

I have it ... 

[Bread80]

The 4MHz PHI is used to generate the clock signal for the data separator in the disc interface (DDI-1 or on board), so I assume you're still clocking that at 4MHz and just feeding a higher frequency to the Z80?

[McArti0]

@Bread
YES! PHI Z80 is one separate Pin only.

Link to emulate Turbo CPC First Level v3

[McArti0]

What should be faster (for add 5 fast clock )...

OpCode	M cycles
PUSH IX	5 to 4
PUSH ss	4 to 3
LDI	5 to 4
LDIR	7 to 5 back to live!!!
CPI	5 to 3
CPIR	7 to 4
ADD A,(IX+d)	6 to 4   (to try 4,4,3,5,3)
ADD HL,ss	3 to 2
ADC HL,ss	4 to 3
INC ss	2 to 1
INC IX	3 to 2
LD SP,HL	2 to 1
LD I,A	3 to 2

JR C,e	4 to 2
DJNZ e	5 to 2
RST p	4 to 3
OUTI	5 to 4

[McArti0]

correction after https://www.cpcwiki.eu/imgs/b/b4/Z80_CPC_Timings_cheat_sheet.20230709.pdf

OpCode	M cycles
PUSH IX	5 to 4
PUSH ss	4 to 3
LDI	5 to 4
LDIR	6 to 5 back to live!!!
CPI	5 to 3
CPIR	6 to 4
ADD A,(IX+d)	5 to 4   (to try 4,4,3,5,3)
ADD HL,ss	3 to 2
ADC HL,ss	4 to 3
INC ss	2 to 1
INC IX	3 to 2
LD SP,HL	2 to 1
LD I,A	3 to 2

JR C,e	4 to 2
DJNZ e	4 to 2
RST p	4 to 3
OUTI	5 to 4

[Prodatron]

SymbOS 4.0b works perfectly.

@Prodatron write benchmark. 

Did you try the SymbOS performance monitor?
https://www.symbos.org/appinfo.htm?00033
The CPU test contains three parts, simple (=LD A,A ), "complex" (=EX (SP),HL ) and 16bit instructions (=ADD HL,xx).
I wonder if the Performance Monitor already show significant differences between a normal CPC and your CPC Turbo.

[McArti0]

Yes, yes, I've already found it. Unfortunately I still have 128kB and 512kB not soldered. Performance Monitor needs 192kB. So now I'm soldering and crying.

[McArti0]

Scope DPOX180H come in.

[McArti0]

CPC Turbo 3 normal clocks + 5 fast clocks has sometimes problem with seek floppy tracks.

I will try to separate ADD HL,SS and set 2 normal + 9 fast clocks.

[Prodatron]

Very interesting! Thanks for posting!
As you can see the Turbo has most effects on 16bit additions and similiar commands. Interesting that there is a difference between ADD A,A:... and EX (SP),HL:...
Your setup looks crazy wild!

[McArti0]

Now SymCALC can be faster 16,5% at 3+5 MHz

SINtest.SCS can be run on SymCALC with TICKS function.

https://www.cpcwiki.eu/forum/applications/excel-for-the-cpc-symcalc-spreadsheet-application/msg244596/#msg244596

[Prodatron]

SymCalc is using a huge mixture of Z80 commands for all this recalculation stuff.
So you have +16% here. Compared to the "complex instructions" (which is just ADD HL,dd ) it is less, so it seems that in the whole process the "simple instructions" are still dominating a lot.

[McArti0]

SkyCHART Star 3magnitudo OldCPC Redraw with precision Math 102sek

CPC Turbo 3+5 Mhz -79sek 130%