Designing a CPLD replacement for the GateArray

Started by SerErris, 15:26, 27 January 22

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SerErris

Quote from: gerald on 13:53, 29 January 22
Too small  ;)
The ink/border registers already require 17*5 bit = 85 DFF. You only have 72.

My first prototype used a XC2C256.


Okay, thanks for the input, I did not have any tool to check if it fits, and also did not know what the driving factor is. That is much clearer now.


What speed grade did your prototype run on? Is the cpld speed critical? Or would it run even on a 20ns grade?
Proud owner of 2 Schneider CPC 464, 1 Schneider CPC 6128, GT65 and lots of books
Still learning all the details on how things work.

pelrun

 If there's any route in the final logic after PnR (which is a heuristic search, so the results are not entirely determined by the input design) that takes longer to settle than the clock period, you'll have problems. Since it depends entirely on what logic is generated; the only way to know for sure is to set the timing constraints in the Xilinx tools and have it check timing closure.

SerErris

I do not think this is a problem, as all the CPLDs in question are in general supported to run with >133Mhz ... This design is pretty slow in running only at 16mhz clock speed.


So I do not think that this is a real issue, but will definately double check in the timing simulation.


Also the Fitter does some work to optimize that as well, but for that it needs to undertand the timing constrains.
Proud owner of 2 Schneider CPC 464, 1 Schneider CPC 6128, GT65 and lots of books
Still learning all the details on how things work.

pelrun

Slower clocks make it easier to achieve, but in and of itself isn't sufficient to guarantee timing closure for all designs. I could write HDL that synthesizes a massively long chain of combinatorial logic that exceeds the timing constraints even on really slow clocks. Which is why you generally want to go wide instead of deep when designing programmable logic, and things like one-hot encoding (which trades off combinatorial logic for increased flipflop use) are preferred. I don't think the GA has anything particularly like that, but the point is it's not hard to get the computer to guarantee it before settling on a part.

SerErris

Quote from: gerald on 13:53, 29 January 22
Too small  ;)
The ink/border registers already require 17*5 bit = 85 DFF. You only have 72.

My first prototype used a XC2C256.


strange ...


@Gerald how many registers does your implementation require when fully implemented?


Mine is 166 .. but I remember (maybe wrong) that it supposed to be 88 ... ???


Something is massively weird with my implementation.

Is it possible that the compiler is acutally adding registers/latches unwanted?


I need to count the registers from the schematic...
Proud owner of 2 Schneider CPC 464, 1 Schneider CPC 6128, GT65 and lots of books
Still learning all the details on how things work.

gerald

Quote from: SerErris on 22:43, 01 February 22
Mine is 166 .. but I remember (maybe wrong) that it supposed to be 88 ... ???
88 is only the ink/border registers. There are many others  ;) 166 is in the right range.

SerErris

#31
Okay .. I counted the schematic.


166 is the exact number of registers (flip-flops).


However Quartus has created 169 out of it ..


In the compilation it first does the analysis and says it is 166, but the final build states 169 ... strange. So the compiler added 3 registers to it, which is propably an unwanted effect, and I need to find out why...

/Edit: The registers getting added by quartus optimzation ... not a concern as long as there are enough logic cells and registers available.
As I a currently compiling on a Cyclone 5 FPGA for code testing, I have plenty of registers and LEs to run this ;-) .



Dedicated logic registers   171   
-- By type:       
  -- Primary logic registers   165 / 112,960   < 1 %
  -- Secondary logic registers   6 / 112,960   < 1 %
-- By function:       
  -- Design implementation registers   166   
  -- Routing optimization registers   5   
Proud owner of 2 Schneider CPC 464, 1 Schneider CPC 6128, GT65 and lots of books
Still learning all the details on how things work.

SerErris

Okay, gentlemen, I still do not have a solution that gives me all the things I want:


1. Fit in the footprint of the DIP-40 socket - the PCB should not be much bigger and directly in there.
2. Support V5 directly without buffers - they are making it even more expensive due to board complexity and additional components requried.
3. Enough PINs on the package (@5V 35 IO pins + 4 JTAG pins (+VCC,GND etc).
4. User programmable without extra components (would make it more expensive).


I have solutions for 3 out of 4, but I cannot get anything together that fits all.


5V is a problem nowadays, so I would most likely need to go with a 3.3V solution, that is at least capable of driving all the control signals. It would still require input buffers (2x10bit) to convert 5.5V down to 3.3V and depending on the CPLD/FPGA device I also would need a second voltage (1.1-1.8V). That creates a lot of components on the board (1-2 Voltage Regulators + the 0.1 caps).


One solution in my mind (now juggling with it) would be based on a Efinix Trion T8 or T4 FPGA. It comes in a 5x5 mm housing providing some 5x IO pins but needs an external flash module. Also it needs two voltages (3.3V and 1.1V).


However it is a small FPGA with a lot of power ... (much more than required). And the package size of it actually allows for small PCB. However it also requires 4layer PCB (or you cannot route all the PINs.

So what I want to say .. it will take a little bit longer to have a working design.

A design based on the old EPM7256AE will also work but requires a larger design. It has the benefit of allowing direct integration into a 5V system without any other things to consider.

I think I will make one prototype of that for me to validate the implementation, but that is also not possible on large scale due to non availabilty of the chips in large scale at low price.



Proud owner of 2 Schneider CPC 464, 1 Schneider CPC 6128, GT65 and lots of books
Still learning all the details on how things work.

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