DiagROM a small MX4 board to attach a diagnostic rom

[SerErris]

Hi everyone,

I started my first project and designed a small ROM setup the DiagROM, it allows to put in a single (E)EPROM to put in the DIAG Rom from @llopis. Thanks for writing it and inspiring me for my first hardware project.



So for now the design is ready and is pretty simple. It just requires 8 components (+2 sockets) to make it happen.
It is specifically designed to fit into an M4 board, but you can exchange the MX4 board just with a connector cable.
I thought long about the point of adding the capability to also run upper rom 0. I do have the space, but I did not see any benefit, as this can be run from any normal rom expansion without any issue.

So it is plain simple now and I am now going into testing mode (breadboard first for the logic, and then ordering some PCBs).

Attached you find the PCB shot + a beauty shot of the board. I could have made the dimension even smaller, but then the routing for the EPROM just looked ugly ... It hurts my esthetics..

[Bryce]

Congratulations on your first project! You could save a lot of PCB by rotating the ROM 90°. Also, mapping a ROM to the Lower ROM 0 position can be done with even less components. The 74LS02 isn't required: https://www.cpcwiki.eu/index.php/LowerROM


Bryce.

[eto]

Congratulations on your first project! You could save a lot of PCB by rotating the ROM 90°. Also, mapping a ROM to the Lower ROM 0 position can be done with even less components. The 74LS02 isn't required: https://www.cpcwiki.eu/index.php/LowerROM


Bryce.

Do you sell those boards? Or are files available to order the PCB somewhere?

[SerErris]

Congratulations on your first project! Also, mapping a ROM to the Lower ROM 0 position can be done with even less components. The 74LS02 isn't required: https://www.cpcwiki.eu/index.php/LowerROM


Bryce.

Interesting. I thought about the idea of just pulling ROMDIS high and simply disable internal ROMS. But I thought it might be good to have a complete implementation that does not interfere with a Upper ROM 0 you want to have on another upper ROM board (such as M4 or MegaFlash or whatever other solution).

But esp. for a DiagROM that could be even cheaper (and smaller):

You could save a lot of PCB by rotating the ROM 90°.

Yeah, I figured that out, even if I was not afraid of PCB space in the first place. However the Mother X4 got me nightmares. The IDC connector is actually not connected correctly - Pin1 of the IDC connector is not Pin1 of the board. The first design I have will not work because of that. So I made a new design with the switched IDC connector, so that Pin50 of IDC is actually PIN1 of the board. @revaldinho do you have any background why you oriented it this way?
I now created a new connector in KiCad. The famous IDC50 Horizontal CPC connector... Instead of Pin1 on the upper right, it is now on the lower left if you look at the male pins.

Do you sell those boards? Or are files available to order the PCB somewhere?

I do plan to build some and can also sell one, but it will get eventually fully open source and you can build your own. Currently I am in prototyping stage and the design is not final. So it will take some time still to get it ready.

[eto]

I do plan to build some and can also sell one, but it will get eventually fully open source and you can build your own. Currently I am in prototyping stage and the design is not final. So it will take some time still to get it ready.

LIKE... but to be honest, I asked @Bryce if his LowerROM PCB can be bought or if the files are public which can be used to order the PCBs. ;-)

[revaldinho]

The IDC connector is actually not connected correctly - Pin1 of the IDC connector is not Pin1 of the board. The first design I have will not work because of that. So I made a new design with the switched IDC connector, so that Pin50 of IDC is actually PIN1 of the board. @revaldinho do you have any background why you oriented it this way?
I now created a new connector in KiCad. The famous IDC50 Horizontal CPC connector... Instead of Pin1 on the upper right, it is now on the lower left if you look at the male pins.

I'm not sure what you mean here.

All the CPC board's I've seen have the IDC connector on the front, component side. For example, see the M4 Board  or XMEM. My boards follow the same convention and plug right into an Mother X4 or any other compatible motherboards.

[SerErris]

Okay here are the new shots :-) ..

[SerErris]

I'm not sure what you mean here.

All the CPC board's I've seen have the IDC connector on the front, component side. For example, see the M4 Board  or XMEM. My boards follow the same convention and plug right into an Mother X4 or any other compatible motherboards.

The point is that Pin1 of the IDC connector is not Pin1 of the CPC anymore ..
https://github.com/revaldinho/cpc_ram_expansion/blob/master/cpc_backplane_edge/pcb/cpc_backplane_edge.v explains it as well ... (if you search for it).

Edge connector:

edge50w  CONN5 (
	.p1 (Sound),  .p2 (VSS),
	.p3 (A15),    .p4 (A14),
	.p5 (A13),    .p6 (A12),

Code Select Expand

// Amstrad CPC Edge Connector
//
// V1.01 Corrected upper and lower rows for male header.

Conn0:


idc_hdr_50w  CONN0 (
	.p50(Sound),  .p49(VSS),
	.p48(A15),    .p47(A14),
	.p46(A13),    .p45(A12),

The IDC connector itself has a Pin1 and the MX4 board has missaligned it. It is not a problem in itself, but you need to be pretty much aware otherwise it will not work.

attached some explanatory pictures. I have created a Kicad Footprint (cloned it) to reflect that.

[revaldinho]

OK - this is just the way the footprints for the IDC connectors are described as provided in the various KiCAD and Eagle libraries. 

R

[SerErris]

I do plan to build some and can also sell one, but it will get eventually fully open source and you can build your own. Currently I am in prototyping stage and the design is not final. So it will take some time still to get it ready.

LIKE... but to be honest, I asked @Bryce if his LowerROM PCB can be bought or if the files are public which can be used to order the PCBs. ;-)

No Problem with me :-) I am not jealous. I developed it mainly for my education and for having a debug rom. If anyone else want to make one. No problem.

And yes @Bryce version does the job specifically for the debug rom and is very easy to build. Actually you only need the eeprom, one capacitor and a resistor and thats it.

If you use it just for the diagnostic rom, you could put it directly on a edge connector. and have therefore a very small and pretty cheap module. The pcb would be the most expensive part in it.

[SerErris]

OK - this is just the way the footprints for the IDC connectors are described as provided in the various KiCAD and Eagle libraries.

R

Yes absolutely. Just saying it confused me ... If I would have looked at your verilog file for the X5 motherboard I would have found out early...

The fun part is .. looking at the verilog file, it looks you did the same mistake in V1.00 ;-)

But now I learned how to do routing in multiple orientations .. And I am glad that the header sits in this hardware as it does, otherwise the routing would be even more painful.

[revaldinho]

The comment is a bit misleading, but I definitely had the inner and outer rows of the connector swapped over on my very first RAM card. The ends of the connector were in the right order though, so I was able to work around the problem by just mounting the connector on the back for that first cut !   

The revised connector and comment have been cut and pasted into all the netlists for my other projects ever since, although the comment only really refers to that original RAM card. I should probably tidy that up.

(Being able to cut and paste know good sections of boards in text from one project to another is one of the reasons I stick with the netlister tool. Very convenient.)

[SerErris]

I see :-) I have a CPC kicad template I use which has the expansion connector fully netlisted and then I can start from there.

Here is my current schematic of V1.01.

As I said I will provide everything under opensource, but want to validate before with a real PCB.

Cheers
Ser

[SerErris]

PCB is on order with JLCPCB. That was the cheapest shipment I could find. The board is so cheap .. 100 of those will cost 18€ to produce. So one will be 18 cent ;-)

[Bryce]

Congratulations on your first project! You could save a lot of PCB by rotating the ROM 90°. Also, mapping a ROM to the Lower ROM 0 position can be done with even less components. The 74LS02 isn't required: https://www.cpcwiki.eu/index.php/LowerROM


Bryce.

Do you sell those boards? Or are files available to order the PCB somewhere?

I made a batch of them a few years back, but I haven't made any since. I don't think I have any left, but I have the layout file somewhere if you want to build one yourself.

Pedantic mode: Lot's of talk here about "IDC" connectors: Neither the MX4 nor SerErris's board contains an IDC connector. I assume you are talking about the 2.54 pinheader.

Bryce.

[SerErris]

I love it, the first time I found out (wikipedia) what IDC actually stands for and the the connector we are talking about is called "shrouded" pin header "with notch key.

And as stated already, the connector on the X4 is (pedantic) not put in in the right orientation. Pin1 of the connector is not Pin1 of the signal path at all. That does not matter but is confusing.

@Bryce do you have the german name for the connector? I always have issue to find them here at the suppliers, because I only know the english terms.

/edit: found it:
https://de.wikipedia.org/wiki/Stiftleiste

[TotO]

PCB is on order with JLCPCB. That was the cheapest shipment I could find. The board is so cheap .. 100 of those will cost 18€ to produce. So one will be 18 cent ;-)

This is the eternal idealistic vision, in the best of all possible worlds. The reality is that you have done the work for incapable peoples out of passion, but who will sell it very expensive on eBay to the detriment of CPC users. ;-)

[SerErris]

If I would want to do a business out of it (which I do not) I actually needed to calculate a lot in there.

My time and effort, shipment cost, component cost, ... something I want to live from ;-).

Luckily I have no time to do a business on that and the business here would be by far to small to actually replace my main job.

And also I question how big the market would be for such a very specialized device that only has two use cases.

1. Run a other OS (need to get complemented by another expansion for other ROMs)
2. Run a diagnostic ROM (how many people actually need that?).

So if I would actually need to make a business out of it, I would stop right here, because I would never get back the development cost.

So I ordered now 10 pcbs. If they are working as expected, I would have 9 for sale. Pricing to be defined. One PCB is around 1€ + components ... so maybe in the 5€ ballpark + shipping.

If you want you post your interest here and I will come back to you if this is working.

[SerErris]

Okay here are some news on this project:

1. I validated the design on breadbord ... pretty chaotic to put over all the cables from the bus, but Mother X4 is helpful for that as well 

2. It is working - So the lower DiagROM is sitting on my breadboard and runs the test ... 

3. The DiagROM is actually Lower AND Upper Rom 0 .. AARG ... how could I miss that  ... 

Now I need get back to the drawing board and consider my options. 
The design works if you have another ROM board of any kind and but the upper rom in there.

But if you only want to have one board with both parts, my bord in current layout cannot support it. 

So I will get back to the drawing table and check what logic I would need to make lower and upper rom selectable and save to operate with other ROMs in the system  (e.g. ROM 1-15). So I would need to put in a ROM selector and that might be overkill. luckily I can do it with a 8in NAND gate and one of the NOR gates, but also I would need to check A13 for and I would need a 1bit latch.  

All of that might be overkill for actually beeing able to have a lower rom board that can run the DiagROM. 

But challenge accepted, lets see how it turns out.

So the current board (still pcb validation required) will work, as long as you have another ROM option for the upper rom. The good thing is, anything will work as long as you have a Mother X4 board.

[SerErris]

Here is the logic for the V2 design:

First part is to latch Rom0 for upper rom selection. This is done via the 8 input NAND which generates high if we have ROM number 0 in D[7:0]. The clock of the latch is generated by checking if both A13 and IORQ are LOW and inverting it (NOR).

The second part then activates OE if either Upper or Lower(0) is selected. Both can be deactivated. 

There is one challenge I cannot get my head around. I cannot find a way do save one nor gate or one inverter. both would remove one chip. So the inverter only has 2 of 6 gates used and the nor has 3 of 4 gates used. 

Anyone spot a way on how to do that?

Alternative I could go with SMD and use a single inverter and use the NOR gate for the other inverter.

[revaldinho]

Yes - don't use the 3 input AND, and instead swap it for a 3 input NOR with a little reconfiguration of the inputs.

AND(NOT(ROMEN_B), A14, Q) = NOR(ROMEN_B, NOT(A14), Q_B)

You have Q_B already available, move the inverter from ROMEN_B to A14 and replace the 3 input AND with the 3 i/p NOR.

Now you have two spare 3 i/p NORs in the same IC and can use those for the two inverters.

No more HCT04.

BUT ...

First part is to latch Rom0 for upper rom selection. This is done via the 8 input NAND which generates high if we have ROM number 0 in D[7:0]. The clock of the latch is generated by checking if both A13 and IORQ are LOW and inverting it (NOR).

.. the 8 input NAND will generate a 0 if all inputs are high, and a 1 if any of the inputs are low.  You need to make an 8 input NOR to generate a 1 only when all inputs are low.

[gerald]

Can I play

 

[revaldinho]

FPGAs and CPLDs are great, but 74 series is much more retro fun! 

It's the way forwards. Or backwards.

[TotO]

Is it really required to disable the low and high ROM separately?

[gerald]

Is it really required to disable the low and high ROM separately?

Yes !
Where is the fun without that option