Creating a replacemant gate array

[McArti0]

all in previews post

[Bread80]

the port address of the Gate Array is dependent address line A15 (and only A15).

Are you 100% sure? 
LOGON wrote that A14 must be Hi.

Good point. I've double checked against the reverse engineered schematics, and it does indeed check A14. I'll update the article. Although I suspect it's more a case of having A14 available and it didn't cost anything to include it, given it's the only internal device which checks more than one bit of the I/O address.

[McArti0]

@Bread80 where is point/edge when GA read VRAM?

[Bread80]

@Bread80 where is point/edge when GA read VRAM?

No idea. That would depend on the properties of the ULA being used and I'm not even sure if those are publicly available.

For the Pico Garry I use point based on the specs for the DRAMs and the timings of the end of the control signals (ie. CAS[0]) do determine when to sample the bus.

• And (I can't remember) if the multiplexers start to change before the end of CAS then that should also be factored in.