Hi,
Jepalza has ported the principe of conception Xilinx 2011 FPGAmstrad version on ZX-Uno, so then I bought on (65€ this little one), and help him realizing a first stabilised version.
https://www.youtube.com/watch?v=tpr9xxx1rsA
ZX-Uno has the same chip size than one I used in 2011 (100% of chip used...). So normaly I can reach the "candidate 002".
http://www.cpcwiki.eu/index.php/FPGAmstrad#Video
It is a very light version (no dsk write access, 640x480, MEM_wr WAITn generator...), but easy to use, and having a clean simple code source (no options addons) that match fully with the FPGAmstrad wiki story.
May interest ones having a ZX-Uno 8)
Efforts done here :
- I removed the pll that was not determinist, and I recalibrated all clocks
- merge of SPI/FAT32 part, SDHC compatible : up to 4GB files inside (can use a 32GB also but filled less than 4GB of files)
- merge of PPI
- merge of interrupts
- page-up key does reset+insert next disk, if you do a continuous pressing it does increment inserting this way a quite of "random disk", after last disk, the first one is re-inserted
- merge of PWM (high quality sound, but mono)
- my joystick is not running fine on my own ZX-Uno, normaly mapped
- keyboard merged
TODO :
- merge of CRTC0
- joystick validation
This makes ZXUno more interesting to buy :D
Another set of efforts done :
- CRTC0 => colors are now fine
- Stereo
- Carousel (robustness around re-inserting disk 1 after last disk)
- Vertical border
- FAT32 erased file detection
And then (no youtube video yet for this next one realise) :
- WAIT_n generator : removed the "MEM_wr" stuff that was invalided until => Arkanoid is then at nice speed, RAM of ZX-Uno are enough robustness
TODO :
- joystick validation
- merge of PPI
- robustness of quick-reset button, whatever games
- display calibration (one pixel h and one pixel v)
I think I can give a little last effort run on it next week. And then normaly I'll got a full merged version (around the "valided" part of FPGAmstrad)
WARNING:Route:464 - The router has detected a very dense, congested design. It is extremely unlikely the router will be able to finish the
design and meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to
completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to
isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issues with the
implementation or synthesis of logic in the critical timing path. If you are willing to accept a long run time, set the option "-xe c" to
override the present behavior.
Intermediate status: 929 unrouted; REAL time: 3 hrs 35 secs
3 hrs 35 secs :'(
Last week I solved a stupid thing slowing down the compilation time around three hours per launch, now it's fine, I'm becoming crazy ???
Now that's a temptation...
https://www.youtube.com/watch?v=CXetrNOD8l8 (https://www.youtube.com/watch?v=CXetrNOD8l8)
Littles updates for this little platform :
- Z80 updated (thanks Sorgelig)
- VGA 800x600@72Hz (because strangly it did shake with VGA 640x480)
Here two CPCRetroDev2019 games running on it 8)
This is really good. I've got a zx-uno, but the CPC cores were a bit of an afterthought. Thanks for bringing this one!