Author Topic: Gate array decapped!  (Read 58541 times)

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Offline rpalmer

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Re: Gate array decapped!
« Reply #225 on: 15:57, 14 May 19 »
Gerald,
The current version of the Gate Array Decapped (both the PDF and verilog) will not work with a CPC6128, but could work with the 464/664.

People will ask what make me say this?
Well checking the the Gate Array PDF and subsequent verilog code shows it DOES NOT output the data lines for the PAL chip as seen on the 6128 schematic. The schematic does not show these as being latched, so it must be within the Gate Array and issued by the Gate Array when accessing memory. The verilog ONLY has the data lines defined as "input" which is the main reason why it will not work as expected on a 6128.

Another issue I have seen with the whole breakdown of the GA is that the 4 MHZ and 1 MHz clock signals do not need to be via the "sequencer". It can be generated through 4 flip-flops. I suspect the sequencer should only be for the handling of reading/decoding and displaying video data.
Attached if a reformatted version (less the 31 colors stuff) with comments where the initial issue lies.
rpalmer

Offline slingshot

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Re: Gate array decapped!
« Reply #226 on: 14:51, 27 January 20 »
1. I'm playing with the schematics and a Verilog translation in a simulator (Verilator). As I see, the sync_n generator doesn't filter out any vsyncs, only shorten it to a duration of 4 hsyncs, if it's too long. But emulators are implementing filtering, like they doesn't start a new frame if there weren't at least about 240 lines. Some demos are depend on it, for example the 4-SINS of the Unique Megademo. You can even notice the blanking mid-frame because of the VSYNCS (the demo issues VSYNCs in 80 lines, and expects 4 such sections in one frame). My question is why does it work on the hardware?
2. Various sources says that VSYNC out is delayed by 2 HSYNCS from the CRTC VSYNC and lasts for 2 lines. However U806 triggers just after 4 hcnts and turns off after 7. Is it right? Looks like it's value is doubled.
3.@rpalmer why should the GA output data? All registers are write-only. Nothing can be read from the GA. It reads from the CPU bus when N244E asserted, otherwise from the RAM.
« Last Edit: 15:54, 27 January 20 by slingshot »

Offline slingshot

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Re: Gate array decapped!
« Reply #227 on: 13:05, 29 January 20 »
Here's a simulation waveform when CRTC issued a vsync (actually a CRTC wasn't wired in, it's just an artifical signal). The length of the vsync in the composite sync seems to be identical to this one:
https://electronics.stackexchange.com/questions/432345/rgbs-sync-signal
Maybe somebody has a waveform capture showing the relation of the CRTC vsync and the GA one?

Offline slingshot

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Re: Gate array decapped!
« Reply #228 on: 15:31, 04 July 20 »
To answer myself, I didn't spot that those counters are not simple binary counters, but follows a strange sequence, because the 3rd stage gets the non-negated output from the previous one.At the end, a Verilog implementation of the GA is finished, and a working core on the MiST and MiSTer FPGAs are released.

Offline robcfg

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Re: Gate array decapped!
« Reply #229 on: 17:42, 04 July 20 »
That’s great news!

Offline slingshot

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Re: Gate array decapped!
« Reply #230 on: 20:48, 04 July 20 »
Here's a corrected waveform capture, which shows the relation of the CRTC VSYNC and the GA VSYNC (and CSYNC) outputs. It can be seen that the HCNT counter looks weird.

Offline VintageAdvantage

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Re: Gate array decapped!
« Reply #231 on: 22:46, 17 April 21 »
Now, how about this idea: if the progress on reconstruction / reengineering is a bit stuck, why  don't we reach out to MEJ

https://ch.linkedin.com/in/markericjones

the original designer... also, the first prototypes used 74LSxxx chips. Anybody know if the first TTL Gate Array was 100% compatible with the later 40007? If so, and we have the 74LSxxx GA schematics (maybe from MEJ), it should be relatively easy to reproduce the whole thing in Verilog / VHDL.

Has this avenue been pursued already? I believe we even have an original TTL GA CPC in the community somehwere... didn't somebody acquire the working CPC 464 prototype, some community member? Reengineering of the GA should be straight forward with that machine!

I don't understand what the current uphold / obstacle is, given the resources available to us: existing TTL prototype, AND original designer still alive (MEJ link above). 

Sorry for my ignorance, I didn't read the whole thread.

EDIT: Likewise, given that there is a Verilog file available, has somebody put that in a chip and in a real CPC to check if it works?  Has the reconstructed / decapped GA logic been confirmed to be 100% authentic? Has this been compared with the "official TTL GA"?
« Last Edit: 23:48, 17 April 21 by VintageAdvantage »

Offline gerald

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Re: Gate array decapped!
« Reply #232 on: 12:06, 18 April 21 »
Nothing is stuck.
Everyone does it at its own pace 

For a FPGA re-implementation from the GA decapping : https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/a-minimal-gate-array/msg198585/#msg198585
As for the verilog version, I don't know. I only use my own VHDL version  ;D

But since you seem to have a lot of energy to spare, why don't you contact the TTL proto and/or owner yourself ?

Offline VintageAdvantage

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Re: Gate array decapped!
« Reply #233 on: 20:54, 18 April 21 »
Nothing is stuck.
Everyone does it at its own pace 

For a FPGA re-implementation from the GA decapping : https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/a-minimal-gate-array/msg198585/#msg198585
As for the verilog version, I don't know. I only use my own VHDL version  ;D

But since you seem to have a lot of energy to spare, why don't you contact the TTL proto and/or owner yourself ?
I think you missunderstood the intent of this question, @gerald - there was no intent to push anybody, but to get an understanding of the status and progress.

 This is a long thread with a lot of technical details. My questions were on a higher level:
  • what is the current status?
  • are we certain that the GA "decapping" yielded a 100% accurate picture of the Gate Array logic?
  • do we have the Gate Array TTL schematics - if so, where? I don't see them.
Yes, I might reach out to MEJ and ask him for the TTL GA schematics if we don't have them.  I don't know, this is why I asked!

Decapping and reengineering seems to be a desperate last step - especially if the designer has not been asked? He must have been asked before going down this rabithole?
« Last Edit: 21:05, 18 April 21 by VintageAdvantage »

Offline tjohnson

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Re: Gate array decapped!
« Reply #234 on: 21:09, 18 April 21 »
Maybe MEJ doesn't have the schematics, worth asking I guess, he might respond, you never know.

Offline VintageAdvantage

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Re: Gate array decapped!
« Reply #235 on: 21:14, 18 April 21 »
Maybe MEJ doesn't have the schematics, worth asking I guess, he might respond, you never know.
Indeed! This is what I was suggesting... why go down this crazy decapping rabit hole business BEFORE ASKING.

Now, without trying to offend or push anybody to do anything here - I'd suggest that somebody who is familiar with the current state of the GA reengineering to talk to MEJ. I myself would not be the right person, because I don't know enough about it.

At that state, it's all guesswork, and "the CPC public community" doesn't even know IF MEJ has been asked. That's what I would like to know. Has he been asked, and if so, what was the result? There is no record of this communication.

Offline tjohnson

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Re: Gate array decapped!
« Reply #236 on: 22:45, 18 April 21 »
You got the contact. Write to him, tell him the issue, provide and link and ask.  No harm in trying he could just ignore you.

Offline VintageAdvantage

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Re: Gate array decapped!
« Reply #237 on: 23:01, 18 April 21 »
Will do!

Offline gerald

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Re: Gate array decapped!
« Reply #238 on: 09:29, 19 April 21 »
do we have the Gate Array TTL schematics - if so, where? I don't see them.
The 40010 is a CMOS gate array. So  no TTL schematic  :D .
But if you look in the thread, you will find a logic schematic.
« Last Edit: 09:31, 19 April 21 by gerald »

Offline VintageAdvantage

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Re: Gate array decapped!
« Reply #239 on: 09:32, 19 April 21 »
The 40010 is a CMOS gate array. So  no TTL schematic  :D .
But if you look in the thread, you will find a logic schematic.
Yes, but the 40007 started as TTL... that should have (had) schematics (somewhere, at some point in time).

Online eto

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Re: Gate array decapped!
« Reply #240 on: 13:14, 19 April 21 »
I was just wondering if the Russian and East-German engineers already did most of the analysis work for us. Both the KC compact and the Aleste 520EX contain logic for the GateArray based on standard logic chips.

I saw that these computers are mentioned in this thread but I think it was not discussed if that logic could be reused. Would it be possible to recreate the gate array from the KC compact schematics? I do not really know much about electronics but the schematics look much simpler to me than the picture of a decapped GateArray. Maybe this question is utterly stupid (which I would understand as I have absolutely low understanding of electronics), then sorry for bringing it up.

Offline RetroCPC

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Re: Gate array decapped!
« Reply #241 on: 16:18, 19 April 21 »
The 40010 is a CMOS gate array. So  no TTL schematic  :D .
But if you look in the thread, you will find a logic schematic.

Has the Schematic been confirmed correct? Has the Verilog code been verified in real hardware?

I've been teaching myself Verilog since the start of the year and it could make a good project...

Offline VintageAdvantage

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Re: Gate array decapped!
« Reply #242 on: 18:50, 19 April 21 »
I've been teaching myself Verilog since the start of the year and it could make a good project...

I saw a picture on a spanish CPC website where a guy had a Xilinx FPGA or CPLD for the Gate Array. There is also a Google Sheet somewhere that shows what was working and what wasn't (I remember Batman demo was working). Not sure if this was Gerald's code that was in his CPLD / FPGA.

I think it would be great if somebody tried with the current Verilog code and put it into a chip to see what it does. But then, only @gerald and others more knowledable on that subject than I can say if that even makes sense at this point, or if it is too early for that.

I must say the Schematics and the Verilog code look quite comprehensible and well documented, great job so far, everybody! Really impressive!
« Last Edit: 18:52, 19 April 21 by VintageAdvantage »

Online TotO

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Re: Gate array decapped!
« Reply #243 on: 19:34, 19 April 21 »
Anybody taking the gerald pdf schematic and redraw it (ISE for Xilinx), can auto-generate the description code in Verilog or VHDL and next clean/rearrange it... Nobody does anything before this reverse engineering work.
« Last Edit: 19:37, 19 April 21 by TotO »
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Offline gerald

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Re: Gate array decapped!
« Reply #244 on: 19:55, 19 April 21 »
I saw a picture on a spanish CPC website where a guy had a Xilinx FPGA or CPLD for the Gate Array. There is also a Google Sheet somewhere that shows what was working and what wasn't (I remember Batman demo was working). Not sure if this was Gerald's code that was in his CPLD / FPGA.

I think it would be great if somebody tried with the current Verilog code and put it into a chip to see what it does. But then, only @gerald and others more knowledable on that subject than I can say if that even makes sense at this point, or if it is too early for that.

I must say the Schematics and the Verilog code look quite comprehensible and well documented, great job so far, everybody! Really impressive!
I cannot comment on the verilog source. I only noticed that has been produced (literally) from the early schematic (which had some errors). I already had the VHDL version started ... and I am not fond of verilog anyway  :P

Was it used for the mcleod_ideafix FPGA's, I can't tell nor bother. The schematic is there for everyone to see an use.

The latest schematic is in line with the VHDL that runs on the board linked above.
On the few issues I had, I came back to the full schematic (paper one, unpublished) and the decapped picture to double/triple/quad check  ??? where I messed up. So I am quite confident that it is a close implementation of the original 40010.


Note that the google sheet seems to relate to a full CPC FPGA implementation, so not something related to the gate array alone.


Offline VintageAdvantage

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Re: Gate array decapped!
« Reply #245 on: 21:31, 19 April 21 »
Note that the google sheet seems to relate to a full CPC FPGA implementation, so not something related to the gate array alone.

This is this one:

https://www.zxuno.com/forum/viewtopic.php?f=59&t=1624
Xilinx XC95216
https://www.xilinx.com/support/documentation/data_sheets/ds068.pdf
There doesn't seem to be anything else on this board... just the pin mapping.

In principle I would also have the equipment to do this... maybe a smaller CPLD with PLCC socket could also do, not sure how many cells it needs. I have used XC9572 before and have the programming equipment (WebISE and platform cable and such). 


« Last Edit: 21:44, 19 April 21 by VintageAdvantage »

Offline revaldinho

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Re: Gate array decapped!
« Reply #246 on: 21:54, 19 April 21 »
There is an FPGA version of the Amstrad CPC which runs on the MiST platform:


https://github.com/sorgelig/Amstrad_MiST


The code is nicely organized in this repository, with all of the gate array modules in its own folder. The code looks like it's a straight implementation of Gerald's excellent schematics.


I just downloaded it and synthesized the GA and the results look promising for a standalone CPLD implementation. Not too many warnings after some minor porting of SystemVerilog code to Verilog, and it fitted easily in an XC95288XL target (~25UKP ea), but it's too big for an XC95144XL (~9UKP ea).


Code: [Select]

cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: ga40010                             Date:  4-19-2021,  7:38PM
Device Used: XC95288XL-10-TQ144
Fitting Status: Successful
*************************  Mapped Resource Summary  **************************
Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
187/288 ( 65%) 400 /1440 ( 28%) 380/864 ( 44%)   130/288 ( 45%) 50 /117 ( 43%)


 

Online TotO

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Re: Gate array decapped!
« Reply #247 on: 22:19, 19 April 21 »
Exactly. The GA core of the MIST and MiSTer are based upon the gerald's schematic (provided into the directory).
Sorgelig does a great job to improve the CPC emulation, as usual for the other systems.
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Offline VintageAdvantage

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Re: Gate array decapped!
« Reply #248 on: 00:23, 20 April 21 »
There is an FPGA version of the Amstrad CPC which runs on the MiST platform:


https://github.com/sorgelig/Amstrad_MiST


The code is nicely organized in this repository, with all of the gate array modules in its own folder. The code looks like it's a straight implementation of Gerald's excellent schematics.


I just downloaded it and synthesized the GA and the results look promising for a standalone CPLD implementation. Not too many warnings after some minor porting of SystemVerilog code to Verilog, and it fitted easily in an XC95288XL target (~25UKP ea), but it's too big for an XC95144XL (~9UKP ea).


Code: [Select]

cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: ga40010                             Date:  4-19-2021,  7:38PM
Device Used: XC95288XL-10-TQ144
Fitting Status: Successful
*************************  Mapped Resource Summary  **************************
Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
187/288 ( 65%) 400 /1440 ( 28%) 380/864 ( 44%)   130/288 ( 45%) 50 /117 ( 43%)


 
Oh, good job...  dare to "connect the pins" and put it into a real CPC?

I have some PLCC prototyping boards, gonna see if I can find a large enough Xilinx CPLD in that packaging format, then I could also try it.



Offline revaldinho

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Re: Gate array decapped!
« Reply #249 on: 10:39, 20 April 21 »
Oh, good job...  dare to "connect the pins" and put it into a real CPC?

I have some PLCC prototyping boards, gonna see if I can find a large enough Xilinx CPLD in that packaging format, then I could also try it.


The XC95288XLs are only available in TQFP packs as far as I know. They're also 3.3V parts with 5V tolerant IOs, so they need a small carrier board PCB with a voltage regulator and decoupling at least.


It's a mini-project, but not one I'm going to take on just yet. I have a few other things in the pipe ahead of that.