Mass Storage (8/16 bit IDE) for CPC464/6128 Project

[TFM]

while reviewing lots of sources, I cannot seem to find a schematic or even a PCB layout for the the IDE8255 - anyone got one handy? - Yarak's site comes back with missing links sadly =(

Well, once I had access to that. Must check my other computer...

However, Yareks solution seems to be very well done. It's not even (todays) fastest, it also provides plugs for hard-disc and memory-card. So no adapter is needed.

IMHO it would be great if we could stay software compatible.

[Bryce]

What I don't understand is that Yarek "hides" his designs behind a registration/password system and isn't part of the scene. He really needs to be more open with his designs and be a bit more active in the scene.

Bryce.

[Gryzor]

Well, there's no accounting for personal psychology. If Yarek feels introverted and does stuff for himself, I guess it's his right, much as it might be to the world's distaste...

[MacDeath]

Heheh just kidding. I've always wanted a C128

C128 is quite nice... sadly it should hve been supplied with more colour palette and perhaps a few more Video modes IMO.


Concerning design, the "little Amiga500 clone" look is nice too.
And as usual I always prefer 8bits with more than 64K.


Oh, and it has a Z80 too (despite slow one)

[TFM]

What I don't understand is that Yarek "hides" his designs behind a registration/password system and isn't part of the scene. He really needs to be more open with his designs and be a bit more active in the scene.

He produces for different computers and has a real life too. His time is limited. But I always got my answers when I emailed him.
It's his decision if he released his schematics or not. It's accepted for any PC hardware producer, it should be accepted for other systems too. But don't get me wrong, sure it would be great to have this data in the Wiki for example.
My guess here is, that he just has not enought time to update his HP. I know he is very busy.

[Bryce]

That's ok, but it doesn't explain why he has everything behind a password.

Bryce.

[Gryzor]

It does: he doesn't feel like sharing

[TFM]

Just get your account! 

[Badstarr]

Last times I tried to register on Yarek's site the links were dead and I couldn't register an account, I had assumed that the site was no longer being maintained. This is why I agree with Bryce, if his ideas aren't shared with the general community then there is always a risk they could disappear forever. It is his choice of course, but if the hardware only exists in isolation then it's almost as if it never did exist.

[TFM]

That's true, it should be moved in the CPCWiki :-)

[Gryzor]

 Ars gratia artis...

[TFM]

Na dann zurueck zum Thema

[KaosOverride]

Hello!!

I am working in an expandable easy I/O board for the CPC, derived from my work of attaching a Wiznet module to our computer. Because I'm using a GAL for address decoding and using only one from 8 outputs to activate the Wiznet I have redesigned it to use more signals and use some kind of cartridges, each one with it's own IO address space (Autoconfig, you plug the hardware cartridge and the slot number gives certain IO range... good for prototiping and not taking care for address decoding...)

Well, one of my cartridges pretends to be an IDE interface, 8 to 16bits data bus, IO space and data port Symbiface compatible. It's a mix between GIDE (2 state GAL based data port) and XT-IDE (Latching/buffering idea derivate) so you don't need the expensive and rare to find exotic buffers from GIDE and don't have the 2 separate data ports from XT-IDE.

I have made a quick independent scheme for an independent interface.

Be careful because:
-It's NOT TESTED
-It's WORK IN PROGRESS
-It's all THEORY
-It's open to suggestions/revisions/rectifications

SCHEME: http://imageshack.us/a/img72/1820/gxide.png

EDIT: New URL... Works?

GAL 1 CODE

Spoiler: ShowHide

TITLE           CPC GXIDE GAL IC1
PATTERN         01
REVISION        03
AUTHOR          Tilmann Reh & KaosOverride
COMPANY         AutoMeter
DATE            27.10.2012

CHIP GIDE1 PALCE16V8

tog1 a0  a1 a2 a3 /wr /rd /selq null gnd
/oe lh /iord /iowr /enta /entb /lout lin tog vcc

STRING CS1ADR '(/A3 * A2 * A1)'                 ; CS1       Addr. x6..x7
STRING DATADR '(A3 * /A2 * /A1 * /A0)'          ; CS0/Data  Addr. x8
STRING TFRADR '(A3 * (A2 + A1 + A0))'           ; CS0/Task  Addr. x9..xF

SIGNATURE TR-GIDE1

EQUATIONS

LH := /LH * /TFRADR                             ; FlipFlop: LSB/MSB toggle,
                                                ; reset at Task File accesses

/TOG = (DATADR+TFRADR) * SELQ * (RD+WR)         ; LH-Clock: Data & Task File

LOUT = DatAdr * SELQ * (Rd+Wr) * LH      ; ena. data out Latch

LIN = DatAdr * SELQ * (Rd+Wr) * /LH      ; reg. data in Latch

IORD = (TFRAdr+CS1Adr+ DatAdr*/LH) * SELQ * RD  ; read accesses to drive

IOWR = (TFRAdr+CS1Adr+ DatAdr*LH) * SELQ * WR   ; write accesses to drive

ENTB = DatAdr * SELQ * Wr                       ; en. Transc. B Enable

ENTA = (TFRAdr+CS1Adr) * (Rd+Wr) * SELQ         ; LSB direct transfer (TFR/CS1)
     + DatAdr * RD * SELQ                       ; LSB transfer (Data)


;ENHI = DatAdr * LH * SELQ * (Rd+Wr)             ; en. MSB output to drive/Bus
;
;ENLO = (TFRAdr+CS1Adr) * (Rd+Wr) * SELQ         ; LSB direct transfer (TFR/CS1)
;     + DatAdr * (/LH*RD + LH*WR) * SELQ         ; LSB transfer (Data)

GAL 2 CODE

Spoiler: ShowHide

TITLE           CPC GXIDE GAL IC2
PATTERN  01
REVISION 04
AUTHOR          Tilmann Reh & KaosOverride
COMPANY         AutoMeter
DATE     10/17/12

CHIP  GIDE2FIX    PALCE16V8

a0 a1 a2 a3 a4 a5 a6 a7 aextra  gnd /iorq
sel exp /cs1 /cs0 ia2 ia1 ia0 /selq vcc
SIGNATURE HP-GIDE2

EQUATIONS

sel = /a4 * /a5 * /a6 * /a7 * /aextra                ; address decoder (50H)

selq = sel * iorq  * (a3+a2)               ; interface access x4..xF

ia0 = a0
ia1 = a1
ia2 = a2                                        ; signal buffering

exp = sel * iorq * /a3 * a2 * /a1 * /a0     ; x4 (22V10 only)
cs1 = sel * /a3 * a2 * a1                       ; x6, x7
cs0 = sel * a3                                  ; x8..xF

It's more complex than the +3E one but it pretends to use existing software

[MugUK]

I saw the Spectrum +3 one being demonstrated at Play Expo last weekend. Looking forward to something similar for my 6128.

(I was the one who pointed out the spelling mistake )

[Zetr0]

@KaosOverride

That's Amazing!

(its also very reminiscent of Pera Putniks 16bit IDE solution for the Spectrum =) )

I shall develop a PCB and a prototype - will this work for future OS as well?

what ROM's will I need

[Zetr0]

I saw the Spectrum +3 one being demonstrated at Play Expo last weekend. Looking forward to something similar for my 6128.

(I was the one who pointed out the spelling mistake )

LOL.... what spelling mistkae.... I dont make mistakes

[KaosOverride]

@Zetr0

It's supposed to be Symbiface IDE compatible, almost mimics same IO port range and it's functions. So you hace Symbos, FutureOS, BonnyDOS and anything compatible with that interface.

Take in mind it can fail, it needs revision

EDIT: This should help, the scheme for Proteus http://www.kaosoverride.net/cpc/hard/easy4cpc/GXIDE.zip  (Again the hardlink fail, you have to COPY the URL to a new windows, sorry)

[Zetr0]

thanks for the link CaosOverride!


What is a .DSN extention ?

[KaosOverride]

The design scheme file for Proteus/Isis 7

[Zetr0]

awesome !

my sincere thanks -

Now off to download some software =D

I have enough bits to put together a rudimentary prototype =)


We could refine this to use a single XC9572XL - we could then include a PS2 mouse connector and possibly a 115kbps Serial interface *although the latter would get interrupted when the cpu clock is interrupted unless its made async.

Hmmm possibly I am a little wired with caffeine and over thinking it... lol

[KaosOverride]

Yeah! Pera Putniks interface is a great piece of hardware, it uses the same 8/16 bits multiplexer as the XT-IDE, which for writing has de handicap to first write the D8-D15 byte and then the D0-8. So you have to switch bytes and take some more time...

But the GUIDE used a GAL for a 2 step writing/reading data in an unique port, but an expensive and rare pair of latch/transceivers. I think I have been able to use some cheap chips based in a heavy redesign of Pera's/XT-IDE's multiplexer and recode the GAL for the new needs

EDIT: relooking the scheme, maybe the OR gates can be reordered to prevent possible timing issues reducing the steps, they are 4 levels for the most complex block...

Maybe
U7A direct output to /GAL1
U7B direct output to /GAL2
U7C A9 and A7 input, output to /GAL3
U7D A6 and A5 input, output to /GAL4
A4 to /GAL5 as is

Same result, but maximun 2 steps/levels of evaluating gates

[Gryzor]

Missed this thread, this sounds promising (I guess), impressive and out of the blue

[KaosOverride]

Soon I will receive the components and I will do tests on a prototype board. I will comment the results here

[Zetr0]

@KaosOverride

I am currently building a prototype from your schematic my friend, but as a Z80 plug-in

with luck this weekend will see me test it in the CPC6128 =)


just got to do a bit of reading up on how to get Symbios and Future OS working =D

[TFM]

Well, to install FutureOS, you just put the four ROMs at ROM selects 10-13. To make it work with IDE, well, depends on your card - I have to update the IDE ROM (5th ROM, still wip).