Mulptipurpose floppy disk controller

[wilco2009]

After some time of development and trials, I'm finishing the details for a new floppy disk controller, valid for an Amstrad CPC + upper ROM interface, a Spectrum +2A/B and a Spectrum 16Kb + my superupgrade interface.


You can see more details in the original posts (Spanish): post1, and post2


The system consists in three diferent boards:


- Floppy disk interface main board
- CPC adapter board
- Spectrum adapter board.


Below you can find some picture of the prototype working with only the main board conected to a Spectrum + 2A, CPC464+Megaflash and Spectrum 16K+superupgrade though a EDGE connector with several cables.


Spectrum+2A








Spectrum 16Kb + Superupgrade













CPC 464 + Megaflash








Mainboad has a 26 IDC conector with all the necessary signals. It is connected to the CPC or Spectrum adapter through a flat cable.


Each adapter consists on a EDGE conector to connect to the computer, a 26 pin IDC connector and a bus extension.


In the case of CPC adapter, I will add a 50 pin IDC connector, to use a MX4 connection instead the EDGE conexion.


See bellow the projected board (it has a error in the with of the bus extender, and has to be corrected):





We are now in the process of ellaborate a list to make an order of boards and components.


My problem is I have not a MX4 board, and I'm not sure about the pinout of the IDC50 connector. Could somebody publish a picture of the EGDE-IDC cable or the pinout scheme?

[wilco2009]

Nobody has a MX4 board to say me the pinout correspondence with the EDGE connector.....?


Is it 1-1, 2-2.......50-50?

[IanS]

Nobody has a MX4 board to say me the pinout correspondence with the EDGE connector.....?


Is it 1-1, 2-2.......50-50?

I don't have an MX4, but from the adapter in another thread it looks to be pin-to-pin. Would seem foolish to do it any other way.
Does this help - DDI clone to MX4 board adapter is done

[TotO]

It's just wirring... That should help you.

[SyX]

@wilco2009: As i told you in ZdP, it's not a problem to help, there is not big secrets here, only ask

[wilco2009]

Thanks a lot,  .


It is that I need.


The final version (At least until now  ) for both adapter board are the following.


CPC





Spectrum





We have to add now ready signal simulation and indepent head selection for DS0 and DS1.


READY SIGNAL:

Code Select Expand


   nREADY = !(!C & !nMOTORON);


   WAIT_INDEX = ! !(nREADY * !nMOTORON);

   A = !(WAIT_INDEX * nINDEX);
   B = !(nREADY * !WAIT_INDEX);
   C = !(A * B);


HEAD SELECTION:

Code Select Expand

nHDSEL = (nHDSW_DS0 + nDS0_SEL) * (nHDSW_DS1 + nDS1_SEL);

[TFM]

Please don't simulate the Ready signal, take it from the floppy. Else a lot of software will have problems.

[wilco2009]

Please don't simulate the Ready signal, take it from the floppy. Else a lot of software will have problems.

The idea is to install a jumper to simulate or not ready signal.
Nowadays many floppy drives does not have the possibility to use Ready signal instead disk change.

In my emulation, i'll try to wait to the first index signal before return ready

[TFM]

Hmmm.... ok, if you wait a minimum time after switching on the drive motors then it should work. You an always check if Symbos of FutureOS work w/o an read error as an reference.

[wilco2009]

OK thanks. I'll use it as reference.
I have added the" ready" functionality for floppy drives with no possibility to generate it.
The Interface generates "ready" signal if motor is on, drive is selected and one Index pulse occurs. "Ready" signal is removed if motor is off.
Emulation can be disabled with JP1.
Additionally I have added two switches to select the Head of each drive separately
The interface works with one or two floppy drives without modification in the drive to select it as DS0.
DS0 drive have to be connected after the cable twist, as is done in the PC's.
Below you can find a picture of the component distribution.

[TFM]

Sounds great! 

[TotO]

I suggest that IC2 is the AMSDOS ROM, and the 74HCT00 allow to decode it?

[gerald]

I suggest that IC2 is the AMSDOS ROM, and the 74HCT00 allow to decode it?

Looks more like the data separator. The ROM does not seem to be part of the design.

I have added the" ready" functionality for floppy drives with no possibility to generate it.
The Interface generates "ready" signal if motor is on, drive is selected and one Index pulse occurs. "Ready" signal is removed if motor is off.
Emulation can be disabled with JP1.

It would be better to generate the ready signal from the index pulse and a timer. If you remove the floppy while the motor is on, the controller still get a ready signal.

[TotO]

Yes, you are right. 
A new design should use the FDC9266 instead.
It embed the SED chip that allow to save room and allow to add the AMSDOS ROM on the design.

[wilco2009]

I suggest that IC2 is the AMSDOS ROM, and the 74HCT00 allow to decode it?

There is no ROM in the design.

You have to take in account it is a generic interface, valid for Spectrum and CPC.

In case of CPC, it needs an upperROM interface as Megaflash.

If you wanna use it with a Spectrum +2A, it is not necessary a ROM, because it is in the computer.
In case of a "spectrum 16Kb", you can use my superupgrade interface. It give to the 16Kb all functionalities of a +2A, and with the floppy interface you can convert your 16Kb in a +3 with the possibility to change to other ROM systems, availables for spectrum.

Looks more like the data separator. The ROM does not seem to be part of the design.
It would be better to generate the ready signal from the index pulse and a timer. If you remove the floppy while the motor is on, the controller still get a ready signal.

Yes, you are right, but it means to increase the board surface in order to add a timer.
I thought on how to handle it and it is possible to use disk_change and motor_on signals to remove the ready signal.

[TotO]

There is no ROM in the design.
You have to take in account it is a generic interface, valid for Spectrum and CPC.

In all cases, this FDC allow you to save space and decrease cost  in your design.

[gerald]

Yes, you are right, but it means to increase the board surface in order to add a timer.
I thought on how to handle it and it is possible to use disk_change and motor_on signals to remove the ready signal.

By 'timer' i was more thinking of a simple RC one, reset (discharded by the index pulse)  and with a RC constant long enough to stay below a gate threshold  for the at least 200ms.

[wilco2009]

In all cases, this FDC allow you to save space and decrease cost  in your design.

OK, It's true, I'll study it for a version "two" of the interface.

By 'timer' i was more thinking of a simple RC one, reset (discharded by the index pulse)  and with a RC constant long enough to stay below a gate threshold  for the at least 200ms.

Mmmm, very interesting idea. It's simple and it left free three pins in my GAL.

[Bryce]

My DDI-2 design (that I still haven't got around to finishing) is based on the FDC9266. I can send you my schematics if that helps? I'll probably never get around to building it myself.

Bryce.

[wilco2009]

My DDI-2 design (that I still haven't got around to finishing) is based on the FDC9266. I can send you my schematics if that helps? I'll probably never get around to building it myself.

Bryce.

Yes. It will be great!.


At the moment, I wanna finish my version with the FDC765, but it could be a big help to develop a new version.


Thank you very much.

[Bryce]

Yes. It will be great!.


At the moment, I wanna finish my version with the FDC765, but it could be a big help to develop a new version.


Thank you very much.

Send me a PM with your e-mail address and I'll send you the files I have (Datasheets etc too).

Bryce.

[wilco2009]

After some work I managed that the simulation signal works properly.


Firstly I have used a 555 and a NOT gate to extend the duration of the simulated /READY pulse.


/INDEX signal was the trigger for 555 configurated as a retriggerable and then the output signal is inverted with a NOT gate.


Reading the description of the signal /READY in a floppy drive manual from SAMSUNG, I thought this had to work, but my suprise was this was not working.


Using the logic analyser and monitoring the real /READY signal from the floppy I found that the behaviour of /INDEX and /READY signal is different as is described in the manual.


The description of /READY signal in the manual is:

-. Ready
This line becomes active "LOW" when the drive is selected, a disk is
clamped and the spindle motor is up to speed.
(after counting at least two Index pulses)
Otherwise this line goes logical "HIGH" level.

But as you can see in the chronogram, the /READY signal is present before /INDEX :


CHANNEL 0: /INDEX
CHANNEL 1: /READ
CHANNEL 2: /READY
CHANNEL 3: /DRIVE_0_SELECT
CHANNEL 4: /MOTOR_ON
CHANNEL 5: /TRACK_00
CHANNEL 6: /DIR_SELECT
CHANNEL 7: /STEP





The only signal present before /READY signal is /MOTOR_ON from the computer, and then is not possible to know accurately the status of the floppy drive without the use of the real /READY signal.


The only possibility is to give a grace period after /MOTOR_ON to be able to get the /INDEX pulses.

The solution was to use as trigger for 555 the following equation:


/TRIGGER = / /MOTOR_ON & /INDEX.


The main difference with the real signal is that simulated /READY signal is low when the drive is not selected, but I think it is not a problem, because nobody check this signal if the drive is not selected. It could be corrected with an additional AND gate but I think it is not necessary.




Finally, this is the scheme of the working design:





Q2, R8 y R9 can be replaced with a NOT gate, and Q3, R10 and R11 with another, while D1, D2 and R3 can be replaced with an AND gate.


With this circuit, /READY signal works as expected, no errors are shown when the access is successfuly done, but "Unit not ready" message appears when the disk is ejected.

[wilco2009]

Guys, I have received the main part of components and the boards and I have made a preliminary assembly.

You can find below some pictures of the result.



Connected to a Spectrum +2A



Connected to a Schnneider CPC464.



A closeup of the board.



And finally my frankenstein.

A Harlequin plus home-made keyboard (with micro-switches) plus superupgrade plus multipurpouse floppy interface.     



As you can see, it is working. :-D:-D:-D

[TFM]

Oh WoW! Awesome work!!! And good do see you back :-)

[jrodriguezv]

Nice work wilco! I hope I can see my CPC using your controller soon :-)