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Preasic/asic dram page mode.

Started by dragon, 13:39, 03 September 21

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We are speaking beginning from these thing cliff Lawson wrote decades ago.

">What did the ASIC in this "cost down" CPC6128 do? Which IC's did it

Pretty much exactly the same as the original 6128 ASIC but I think it maybesoaked up a few of the external TTL as well. It's main reason for being wasto allow the use of page mode DRAM which was replacing the rather obsoletetype in the original 464 design. That modern type of DRAM was also reducinghugely in price because of it's wide use for PCs.

We found gerald write something years ago about that cpc used that mode to write video ram.
But, exactly how it wok?. The preasic/asic can support ram with/and without dram page mode?. Or only with page mode?
How he can know what mode use?.


Not sure about the lack of page mode on the original design excuse  :D .
The gate array IS using page mode to read 2 consecutive byte between every Z80 dram access cycle.
The main difference between the dram you can use in the cost down / Plus is that they store 4 bit instead of 1 and use a bi-directional bus for data instead of dedicated datain and dataout.
The point is that the gate array can't manage the bidirectional databus without modification and/or additional HW.

So my guess is that in search of a lower manufacturing cost, re-doing the GA for using these new and cheaper ram ended up in the pre-asic, which at the end included far more than that (CRTC, dram MUX).

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