The MegaFlash

[TotO]

DISCKIT3 ? 

[dragon]

I have the wilco version. And I have problem with it. In first time it not work(basic repeat many times in all slots).I solve it repasing edge 50 connections to the motherboard o megaflash. And it work, but after a litte time i testing  it, they can't erased a rom, and copy the basic cpc internals rom returns me "I" in the new slot.(and corrupt rom of course).And later nothing, not write, not erase, but he can read the content of the external flash.

I tested all lines with multimeter with help of the schematic, and nothing all lines and 50 edge connection is o.k,so no cut tracks in motherboard.

¿Can be a Ic problem?. cpc connector appears fine :S.

[Bryce]

Sorry, I don't know or support any version other than the original, so I can't really help you, but maybe some other users here can?

Bryce.

[dragon]

Sorry, I don't know or support any version other than the original, so I can't really help you, but maybe some other users here can?

Bryce.

Do not worry bryce, It was just to ask for another opinion,I've put here for not make a new post.

[TFM]

What exactly is the problem?
Which function does not work?


Sorry for asking, but your post is a bit confusing.

[Bryce]

Do not worry bryce, It was just to ask for another opinion,I've put here for not make a new post.

No problem. Hope you get it sorted.

Bryce.

[dragon]

What exactly is the problem?
Which function does not work?


Sorry for asking, but your post is a bit confusing.

No problem.

summarizin:


1. I solder all components in the motherboard.-> Megaflash not work(all slots rom are the basic rom copy) ->The cause is a bad weld in the 50 way connector to pcb.
2.Again I solder the connector, it works perfect, it erase and copy and view the eeprom->Solved.

3.After a two minutes of test. Megaflash not erase the roms, I Do the operation and nothing happen.
4.I test copying internal basic rom to slot 2 for example. He copy a rom in slot 2 named "I" instead of "basic" original name and the rom is corrupted.
5.In another more two minutes he not copy anything. I select copy basic rom to slot 2(empty) or other, and slot 2 is empty(FFFF) after operation.

6.I test all tracks of the motherboard with a multimeter. All are connected, no errors including the 50 edge connector.

7.If I burn a basic slot with the programmer, the megaflash see the basic rom and cpc can run it from the eeprom. but he can't copy it to other slot or delete it.

8. Load a rom from disk to eeprom, not work. result is empty in destination slot (FFFFF) Nothing change.

that's all I've tried.

He not delete roms copy or move it to another slot.But he can  see and use the roms.

[TFM]

Some ideas:


- Try so switch SDD off, to unprotect the Flash. Maybe it got switched on by accident.


- Could it be a problem of working temperature? Try again and check if problems only happen after some minutes of operation.


- Some chip may have a wobbling connection. Or maybe a pin is not clean.


That's just some ideas. I really hope you will fix the problem.

[dragon]

Very strange,today he work(after time later the  cpc is on) i burning a basic rom with the programmer and i unprotect the eeprom in cpc side and works perfect,clear roms and save roms.

I not  touched nothing, and later... same, first errors copy, basic=I. And little time latter nothing, no copy,no save,unprotect no effect...

[Gryzor]

You don't happen to have a ZX next to it, right? All sorts of illnesses could pass over...

[TFM]

Very strange,today he work(after time later the  cpc is on) i burning a basic rom with the programmer and i unprotect the eeprom in cpc side and works perfect,clear roms and save roms.

I not  touched nothing, and later... same, first errors copy, basic=I. And little time latter nothing, no copy,no save,unprotect no effect...

Ok, I'm not the hardware guy. But it could be a heat problem. Maybe one soldering point is cold, I mean not good. Or the heat slightly moves an IC and it looses contact to a pin.


Or ... does you neighbor owns a c64? (Bad energy).

[FRAGKI-2012]

congratulations!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
you are the best !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

[pelrun]

Kudos to Bryce for this board, it'll be a great addition to my CPC. But unfortunately the schematic and board layout are a mess, and the pcb won't be accepted by my pcb fab because it violates DRC clearance checks hundreds of times.

So I've started laying it out from scratch in KiCad. (pelrun/megaflash · GitHub) After a couple of hours of laboriously tracing the spaghetti (manually drawn buses uuuurk) I've got a schematic I can follow without getting a migraine. I'll probably tweak it a bit before I start routing the board, but I'm mostly happy with it.

[IanS]

Looks wrong, the inputs to U3/4 in the lower right should be data lines, not address lines.

PulkoMandy on pushnpop went through the same process of redrawing it, have a look on there, or I'll see if I can find it.

Edit, my mistake, the Ax address lines are from the latch.

[Bryce]

Your supplier must just have lower limits to their production. The BRD I've posted is exactly the same file that went to my supplier for the production run, so it's definitely buildable.

Send me the exact files you tried, maybe they've got corrupted or something.

Nice KiCAD layout though

Bryce.

[pelrun]

Nah, they weren't corrupted. I use a cheap fab, so the minimum clearances are larger. There's no reason to need smaller clearances on the original layout, plenty of room was available for the traces to stay clear of the pads but it wasn't used. That gave me an itch I needed to scratch

[Bryce]

The supplier I use supplies their own DRC file to route and check the PCB. There's also no need to re-do the entire schematic, if you set the parameters for your supplier in the Eagle DRC settings then you just need to re-route it. I chose to go for much thicker tracks and smaller clearances to make it more robust. Some users throw all their PCBs into one box and thin tracks can easily be broken, thickening them up (the MegaFlash has 0.3mm tracks, double the minimum required) will hopefully help it survive such treatment.

Bryce.

[Gryzor]

...and that is a good thing

[pelrun]

Unfortunately I don't use Eagle - I decided I didn't want to relearn how to do simple tasks in it after the third time forgetting, and all that work for a tool that I'd have to pay for if I wanted to do any real work in. If I'm going to pay for an EDA package, it'll be Altium.


Anyway, I'm actually considering tossing out the discreet logic and sticking a $3 CPLD in there instead.

[Bryce]

Yeah, I can understand not wanting to learn another new software package. Is there at least an import feature so that you don't have to put it all in again manually?

The freeware version of Eagle actually gives quite a lot of scope. Most 8-bit projects that I know of for the CPC and other machines could be done with it, but projects that need a bigger PCB are obviously a problem.

Yes a CPLD would make more sense, but I'm a bit of a traditionalist and I wanted to keep everything about it as retro as possible. I know, I'm mad. I also wanted that others could build it themselves without needing any additional programmers or whatever.

Bryce.

[pelrun]

Not readily. In any case, I've already done all the layout except for the decoupling caps. I finished it just as an exercise, I doubt I'll actually build this one.


Now I get to bang my head against the Xilinx tools (tomorrow, I've got a raging headache atm.)


As for programming a CPLD, I'm tempted to see if I can program it from the CPC... 

[Bryce]

As for programming a CPLD, I'm tempted to see if I can program it from the CPC... 

Admit it, you like to punish yourself don't you?

I see you went for SMD parts. Couldn't you reduce the PCB size much more now?

The electrolytic cap is going to get in the way of the 50way header connector? Or is the header on the other side?

Bryce.

[pelrun]

Haha, maybe.


Yeah, the header is on the reverse side, it's not obvious from that angle. And I certainly could make the board more compact, but like I said, this was really only an exercise, and I got as far as I wanted to.

[pelrun]

Oh man, why didn't you tell me my address decoding logic was wrong? 


Couldn't figure out why the address lines coming out of the latch were scrambled... it's because the lines going into it were 

[IanS]

Oh man, why didn't you tell me my address decoding logic was wrong? 

I did find it odd that you had multiple signals that were very different. e.g. A14 is from the CPC and one of the outputs of the latch.

This is the circuit as re-drawn by PulkoMandy on PushnPop. It maybe useful as a double-check.