The MegaFlash

[Bryce]

Oh man, why didn't you tell me my address decoding logic was wrong? 


Couldn't figure out why the address lines coming out of the latch were scrambled... it's because the lines going into it were 

I didn't look that close at your schematics to be honest. I assumed you'd copied mine exactly.

Bryce.

[zeropolis79]

Wouldn't mind having one of these for my 6128 with busted drive.. Can I purchase ready built ones?

[Bryce]

Unfortunately I've already sold the last one and there's no new batch planned at the moment. There have been some clones made of it, so you may be still able to get one of those there. Someone here will point you to the latest/best choice etc, I don't keep track of these things.

It's doesn't replace the drive though. You'll need a HxC for that.

Bryce.

[pelrun]

I didn't look that close at your schematics to be honest. I assumed you'd copied mine exactly.

I wasn't really expecting someone else to check my work - I was just facepalming after understanding the problem. I think I just got crosseyed tracing the original schematic at one point and assumed that D(7:0) was wired signal-for-signal to the latch, and not reordered for routing like everything else on the schematic was


Certainly makes the VHDL I'm writing simpler, it looks something like this now:

Code Select Expand



  A(18 downto 14) <= std_logic_vector(rom_num(4 downto 0));
 
  rom0sel <= '1' when (rom_num = 0) else '0';
  rom7sel <= '1' when (rom_num = 7) else '0';
  romvalid <= '1' when (rom_num < 32) else '0';
 
  selected <= ((rom0sel AND ROM0EN) OR (rom7sel AND ROM7EN) OR NOT A15) AND romvalid;
  ROMDIS <= ((ROMEN AND NOT nRDWR) OR (MREQ AND nRDWR)) AND selected;
 
  WREN <= WR AND nRDWR; -- only allow writes if nRDWR switch on
 
  gate <= IORQ AND WR AND NOT A13; -- A13 low, &DF00
 
  latch: process (gate)
  begin
    if gate = '0' then -- latch on falling edge
   rom_num <= unsigned(D);
    end if;
  end process;

[pelrun]

I did find it odd that you had multiple signals that were very different. e.g. A14 is from the CPC and one of the outputs of the latch.

The net names and the pin names are independent. A14 from the CPC is not connected. The outputs of the latch are actually the high-order bits of the address, A14 to A21, that go to the flash. Since the flash is only 512k, A(21:19) are only used to keep the megaflash disabled if the rom selected is out of it's range.

[IanS]

The net names and the pin names are independent. A14 from the CPC is not connected. The outputs of the latch are actually the high-order bits of the address, A14 to A21, that go to the flash. Since the flash is only 512k, A(21:19) are only used to keep the megaflash disabled if the rom selected is out of it's range.

Still looks potentially confusing, there are two signsls labelled as "A14", which are not the same thing.

If you are going down the CPLD route, have you investigated the option of being about to read from the flash when in write mode (makes it possible to identify the flash type in software and adapt the programming algorithm to match). How about making the write mode software selectable, either via a different port number, or using a higher rom number (which is what I do) e.g. if D6 is high, the rom can be written to.

[Bryce]

I considered that back when I developed the MegaFlash, but I decided against it, because I wasn't sure if it would cause problems on a CPC+ when it accesses the cartridges and I didn't own a plus at the time to try it out. Or whether there were any other expansions that might cause the Flash to corrupt. So in the end I went for a physical switch so that the owner knows exactly what mode the MegaFlash is in.

Bryce.

[MacDeath]

Anyway, the X-MEM from Toto seems to be available, not sure he can ship to australia though..
gotta ask him first...

[pelrun]

Still looks potentially confusing, there are two signsls labelled as "A14", which are not the same thing.

If you are going down the CPLD route, have you investigated the option of being about to read from the flash when in write mode (makes it possible to identify the flash type in software and adapt the programming algorithm to match). How about making the write mode software selectable, either via a different port number, or using a higher rom number (which is what I do) e.g. if D6 is high, the rom can be written to.

Actually there's only one A14 signal, the other is a pin label that has no meaning in the schematic. In any case, which A14 pin do you want to refer to? There is one on both the extension connector and one on the flash part, and they aren't connected to each other. There *are* two independent A15 signals in the schematic, though, which is why one of them is named A15EXT.


I could certainly implement a software write switch, but I tend to agree with Bryce's reasoning. Also direct compatibility with the existing multiflash utilities doesn't hurt

[pelrun]

Awww yeah, new layout almost done, just need to figure out box/mounting holes.


Routing becomes almost trivial when you can reorder the pins to what is most convenient. My biggest challenge was figuring out a way to program the CPLD from the CPC without adding extra address decoding hardware.

[IanS]

I could certainly implement a software write switch, but I tend to agree with Bryce's reasoning. Also direct compatibility with the existing multiflash utilities doesn't hurt

I suspect you could add read support when in write mode without breaking megaflash compatibility. Any existing megaflash compatible software just assumes it can't read.

Which CPLD are you using?

[pelrun]

Pretty much the cheapest/smallest one I can get - an XC9536. It's easily big enough for the megaflash logic with plenty of gates left over.


Read-in-write-mode is just a matter of always using /ROMEN as input to the ROMDIS/CE logic instead of switching between it and /MREQ, I assume? That would be a trivial change.

[IanS]

Read-in-write-mode is just a matter of always using /ROMEN as input to the ROMDIS/CE logic instead of switching between it and /MREQ, I assume? That would be a trivial change.

You can't just use ROMEN when writing as the gate array doesn't assert ROMEN (it thinks the rom is read-only). So you need to use <rom selected> & WR & MREQ.

It's also worth putting A14 into the CE logic, so the chip only gets enabled when a >=&c000 address is selected. Otherwise writes to addresses between &4000 and &7fff will also enable the flash chip.

[pelrun]

Ah, ok.


I found pulkomandy's flashgordon readme, which mentions the A14 issue, so I've already routed that in

[TFM]

It's also worth putting A14 into the CE logic, so the chip only gets enabled when a >=&c000 address is selected. Otherwise writes to addresses between &4000 and &7fff will also enable the flash chip.

Software should - however - always consider both cases.

[pelrun]

Yup, since there's no guarantee the end user has got a peripheral with full decoding or not, or if he even knows the difference.


Anyway, I've finally finished routing Megaflash Redux v1. Time to bite the bullet and send the gerbers out.


Schematics and layout are up on my github. VHDL project to follow.

[Bryce]

You're sending it out for production without having built a prototype? That's brave.

How many do you intend producing?

Bryce.

[pelrun]

Production? Haha, no. I'm just getting prototype pcbs made, it's only $20ish for 10 at this size (yay China). FAR less hassle than etching boards myself.


As for quantity, I dunno. I'd probably make up 10, just because that's the first price break on the parts at digikey - and really, shipping to australia makes buying smaller quantities not worth it. After that it just depends on demand (is there any?).

[CraigsBar]

Heheh yeah, got a few myself. I don't remember if I've got any sealed Amsoft disks though...

I've got some still sealed jewel cased amsoft discs. And plenty sealed soft case maxell. I cannot ever see me using them...... Or selling them.... Just in case.

[TotO]

I've got some still sealed jewel cased amsoft discs. And plenty sealed soft case maxell. I cannot ever see me using them...... Or selling them.... Just in case.

I'm interested for new games, like R-Type was.
Please, contact me.

[pelrun]

I sent out the files to make the pcbs, and an hour later found a big error    Oh well, it's v1a now, and I'll get some drink coasters

[Bryce]

That's a real bummer when that happens. That's why I triple check everything before I send it out.

Bryce.

[TFM]

Time to write some IC simulator software for the CPC ;-)

[pelrun]

Oh, I checked everything thoroughly. It was just that I thought I could get 5v XC9536's, but all I can get are 3.3v XC9536XLs. Which means an extra regulator and some caps, not something I can fix with a greenwire mod. Oh well I'm also budgeting for at least one more board respin in case I find some issues with the prototype.


Anyway, it looks like I'm going to be able to sell these for AUD$50 each plus shipping. And the AUD is pretty weak against the USD these days (*sigh*) so it's something like US$46.

[Bryce]

Time to write some IC simulator software for the CPC ;-)

In my innocence I tried to write a schematic layout program on my CPC in BASIC when I was a kid. Needless to say, I didn't get far.

@Pelrun: You may not be able to find 5V XC9536s locally, but they are certainly still available. I bought a few just recently (can't remember where though).

Bryce.