CPC four times faster...

[Bryce]

Does anyone know what the fastest Z80 currently on sale is?

20Mhz. !!! 5 Times faster.

II'm currently designing an extension for the 6128 in the onebyte cache for write concept.

The eZ80 runs at 50MHz, but the architecture has been optimised, so compared to a standard Z80 it would be equivalent a Z80 at 150MHz.

Bryce.

[McArti0]

eZ80 runs at 50MHz,
Bryce.

But. Z84C0020PEG is real Zilog, pinout compatibility and protocol. I think it is a good replacement even just for reducing the power supply.

[Bread80]

Building an Amstrad with an eZ80 would be fun. A couple of challenges with it though:

* The on device hardware uses I/O addresses starting at $80 (the high byte is ignored). You might have to patch software to avoid those addresses. Most software probably loads those bits high, which would be safe, but writes to the gate array have the register data on those bits. Register 2 could be problematic here. Although I think just setting bit 5 high should solve any issues.

* The eZ80 has no memory manager on board. That means you'll need to use external RAM and ROM. At 50MHz the clock cycle time is 20ns[0]. The fastest parallel RAM chips available appear to be about 10ns. The fastest ROMs about 55ns. Once you add in gate delays for whatever you're using for the memory manager (CPLD, FPGA) you're unlikely to be able to run at full 50MHz clock speed even reading from RAM.

But those issues aside, it's certainly do-able and, as I said, would be fun <g>.

A 20MHz Z80 on the other hand would be far easier. You'll need to replace the DRAM with faster modern SRAM and rejig the gate array timings. But neither of those overly complicated.

• I'm assuming here that the read cycle is a single clock cycle. It certainly is for internal memory. Either way you'll need that single cycle read for the best performance.

[zhulien]

Just curious, the Terasic T-Rex can run the CPC at 24Mhz and it seems pretty reliable - I know it's an FPGA core, but from a timing point of view in relation to a real CPC, timing seems to always come up as an issue - what exactly are the parts of the real CPC that the timings have issues with and which can be overcome on real hardware somehow - i.e. raster RAM chips? faster ROM chip? (I'm guessing)... and why don't such FPGA cores have timing issues even if internally?

[McArti0]

what exactly are the parts of the real CPC that the timings have issues with and which can be overcome on real hardware somehow - i.e. raster RAM chips? faster ROM chip? (I'm guessing)

1us Divided into z80 1/4 time GA 3/4 time to read 2 bytes. A simple speed 2x increase results in too much data to display. Either 100Hz frame and 600Hz interrupt, or change GA to only download 1byte for 1 nop. ROM you can replace FRAM. 

[zhulien]

what exactly are the parts of the real CPC that the timings have issues with and which can be overcome on real hardware somehow - i.e. raster RAM chips? faster ROM chip? (I'm guessing)

1us Divided into z80 1/4 time GA 3/4 time to read 2 bytes. A simple speed 2x increase results in too much data to display. Either 100Hz frame and 600Hz interrupt, or change GA to only download 1byte for 1 nop. ROM you can replace FRAM.

Does that mean if a replacement GA was made with a microcontroller then that could fix the timing issues with the GA?

[McArti0]

YES. New CPC with new GA sponsored by microcontroller

[andycadley]

what exactly are the parts of the real CPC that the timings have issues with and which can be overcome on real hardware somehow - i.e. raster RAM chips? faster ROM chip? (I'm guessing)

1us Divided into z80 1/4 time GA 3/4 time to read 2 bytes. A simple speed 2x increase results in too much data to display. Either 100Hz frame and 600Hz interrupt, or change GA to only download 1byte for 1 nop. ROM you can replace FRAM.

Does that mean if a replacement GA was made with a microcontroller then that could fix the timing issues with the GA?

Well if you change the CPU, change the Gate Array, possibly change the RAM speed, possibly change the motherboard because various electrical interference issues might arise at higher speeds then yes, you could theoretically run a faster CPC.

[zhulien]

YES. New CPC with new GA sponsored by microcontroller

Is it not easily possible with existing cpc and new GA?

You answered this question while I was typing it

[McArti0]

Well if you change the CPU, change the Gate Array, possibly change the RAM speed, possibly change the motherboard because various electrical interference issues might arise at higher speeds then yes

Or maybe we can do it with FPGA? 
OK, the T-Rex is ready. 

[Prodatron]

Or maybe we can do it with FPGA?
OK, the T-Rex is ready.

I just recognized that I still have the T-REX Quartus Snapshot by Tobiflex here on the site:

http://www.symbos.org/download/cpctrex-quartussnapshot10.zip

Feel free to use it, it's only 18 years ago (I have no idea about this VHDL and whatever stuff at all)

[ZorrO]

eZ80 does not support forbidden commands, so it will hang in CPC. R800 would be better. But overclocking the clock is asking for trouble. Image out of sync, FDD is physically spinning too slowly, etc.

[andycadley]

Well if you change the CPU, change the Gate Array, possibly change the RAM speed, possibly change the motherboard because various electrical interference issues might arise at higher speeds then yes

Or maybe we can do it with FPGA?
OK, the T-Rex is ready.

Well yes, if you just build a "CPC on a chip" inside an FPGA that will also work,but it isn't really "upgrading a real CPC" at that point, is it?

The moment real, 1980s hardware is involved, you have to start considering the actual physical limitations of what already exists. It may just not be possible to run something faster without actually redesigning everything.

[Prodatron]

It's interesting that this was different for several system:


- CPC: In general it's impossible to increase the clockrate; RAM is 2MHz, so because of the video it limits the Z80 to 1MHz memory access; everything else is connected to the same clock inside the CPC as well
- MSX: Why not? Until today you can double the clockrate from 3,57 to 7,1 MHz with a standard set of parts, which you can still buy
- Enterprise 64/128: You can even choose between original 4,6,8 or 10MHz Z80 speed; works great!
- C64: You could attach a CMD SuperCPU (MOS 65816) running at 20MHz with own memory; yes, not a C64 anymore, turning the original hardware into a zombie system, but some people liked it

[andycadley]

I think the MSX and Enterprise designs put more effort into decoupling the hardware from the CPU. It had the advantage of making it easier to swap out components and change the performance of various bits without causing as much hassle. The downside is that it's harder to exploit the raw performance of the system because you can't really "hit the metal" in quite the same way (or if you do compatibility strikes hard).

The C64 wasn't really like that but the SuperCPU is a weird beast that treats the host machine more like a kind of slave - a bit like Tube processors on the BBC. You could probably do something like that on a CPC, run everything externally and use the "Z80" cycle to allow the external system to write to video RAM but it would feel like a very different kind of machine.

[zhulien]

TThe vampire method for cpc should be possible which is likely somewhat similar for the turbo chameleon right?  That is put another cpu in it (fpga or not) and use whatever cpc hardware can be used. Cpm could be patched to run really fast, basic perhaps to a degree but most other software wouldn't benefit.  The turbo chameleon and vampire seem to further to emulate almost the entire system,  like putting a trex into a cpc and running the software on the trex but with some type of trex to floppy layer and keyboard layer.

[McArti0]

If you insert 41256-60/70ns, you could reduce the screen data reading time from 3/4 us to 1/4 us or 3/16 us. Then you could read the screen data every 4 cycles with a clock of 16Mhz .

[andycadley]

If you insert 41256-60/70ns, you could reduce the screen data reading time from 3/4 us to 1/4 us or 3/16 us. Then you could read the screen data every 4 cycles with a clock of 16Mhz .

Theoretically, maybe. But you're making the classic mistake that people who focus on the digital aspect always make: you're ignoring the analogue aspects.

There always well be numerous other issues that need resolving as you increase speeds. The bus was designed to tolerate the speeds it was intended to run at, capacitors were chosen for various points of the board because they feel within required tolerances etc. It doesn't necessarily follow that just putting in faster digital components that all the rest of the circuitry will just work (and even less that it will work reliably).

[McArti0]

When I made an ISA 8MHz card with 8255, ADC and etc., I ignored the capacitors and it worked.

You can bargain down to 12MHz or even 8MHz. 

I think SymbOS would be happy. 

[zhulien]

Has anyone actually tried massively overlooking the cpc.  I am thinking the most compatible solution would be some type of cpu accelerator inside the cpu socket with its own ram and potentially its own alternative bus and the ability to programmatically switch between standard cpc mode/ram/speed and its own, but... even in thinking along this method, I think the cplink card is currently the best option. It allows you to run stuff on the pi, subroutines and use the pi hardware indirectly.  Absolutely not a lot of software yet that uses it, but I am having fun with it. 

[McArti0]

And MiSTeR is not a ready-made product?

[GUNHED]

IMHO a hardware-clone/CPCnext/ ... should at least provide the 50 pin expansion port or (maybe even better) some MX4 slots for expansions with MX4 plug.

BTW: I have a CPC6128 running at 6 MHz stable. Just replaced the 16 MHz crystal by a 24 MHz one.

[McArti0]

I have a CPC6128 running at 6 MHz stable.

what RAM do you have 150ns?, mux LS153? what CRTC, what 8255.
Take a photo of the mainboard that RUN.

and check the temperature of all chips, especially 765