can expansions talk to IO devices?

[martin464]

Hey dumb question
can an expansion talk directly to another IO device, if it had control of the bus
like could it send data to the PPI chip?
or would some of the cpu signals be driven the wrong way like IORQ and risk damage?
Martin

[Bread80]

Yes. You need to send the BUSRQ signal to the Z80 and wait for it to send BUSRQ. At that point it will have tri-stated all(?) its outputs and you can drive the bus. You'll need to consult the Z80 docs for full details.

[McArti0]

Manual z80:
"BUSREQB us Request (input, active Low). Bus Request has a higher priority than NMI and is always recognized at the end of the current machine cycle.
BUSREQ forces the CPU address bus, data bus, and control signals Marea, IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. BUSREQ is normally wired-OR and requires an external pull-up for these applications. Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing
dynamic RAMS."

[McArti0]

How write to internal memory? nMREQ L, nRD H and all? what,s with M1? Why GA wants M1?

[martin464]

oh yeah that's nice to know about thanks for that!

[Bread80]

How write to internal memory? nMREQ L, nRD H and all? what,s with M1? Why GA wants M1?

Just MREQ and WR or RD should do it. But the GA gates those signals so they only happen during the CPUs portion of the video cycle. You'll probably need to investigate the CPU, MWE and RAMRD signals along with CAS to get your timings accurate. And you'll need to consult the datasheet for the DRAMs to ensure you're asserting signals and data, and the GA is asserting signals (and therefore data) in a way which doesn't violate any timings.

The best strategy for doing this would probably to hold the data and signals for an entire video cycle (ie. 1uS) to ensure the GA has time to do it's thing.

As for M1, the Z80 asserts it along with IORQ as the 'interrupt acknowledge' signal. The GA uses that to clear the interrupt flag and signal. I think the GA also uses it during reset.

[McArti0]

https://github.com/codedchip/AMSGateArray/blob/master/Docs/40010-simplified_V03.pdf

Ok. Full knowledge. all clear.

[rpalmer]

Devices can talk another provided it does not conflict with other I/O channels where the device has control.
In this case the Video GA may control of the data bus for the CRTC, in which case there could be a data bus conflict as external devices will not be able to know if the bus is under control of the GA.

[andycadley]

You'd have to respect the timing available to the CPU under normal circumstances. So you could disable the Z80 and take over the bus, as long as you only use it for the periods the Z80 would normally be allowed (accessing GA registers at that point should also be safe, because the Z80 could have done so too).

[McArti0]

Ok. GA is "AlwaysReadWriteMachine" for bus.

AutoRAS_AutoCAS_AutoREADY_AutoWR machine.

when nRD is const Hi, the memory is written cyclically at a frequency 1MHz. nMREQ not needed ? , need Lo ?

when nRD is const Lo, the memory is read cyclically at a frequency 1MHz but without joining result to bus.

nMREQ is const Lo, result read memory is joining to bus and changing when GA READY has edge UP. True result is when  GA READY has edge Down.

[McArti0]

Live Emulator GA. Memory control only

When nMREQ is Hi, CAS not present.