Z80 CPU+Gate Array timing ...

[McArti0]

Some interesting and surprising discoveries...

based on a comparison of @Bread80 diagrams with the Z80 manual.

https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/

https://www.zilog.com/docs/z80/um0080.pdf

Did you know that CPC may not have 4 clocks per cycle?

[pelrun]

The "4 T states per operation" thing only applies when the Z80 is in phase with the GA, and the memory access window (READY high) lands in either T2 or Tw.

Once they're in phase, in *normal operation* they'll stay in phase.

The trace you have shows the window landing on T1. So it's not in phase at the start of the trace.

To actually get into phase (on startup, or if there were external shenanigans) requires the extra couple of T-states to go somewhere. But it's a singular occurrence, and by the time your code is in a position to be doing literally anything, the Z80 will be in lock-step and your timings will be as expected.

[McArti0]

There are definitely some 4-clocks opcodes that sync GA with z80. But are there opcodes that desynchronize z80 from GA? And does the 40007 work exactly the same as the 40010?
The diagram from read IO is even more puzzling.
7-clocks cycle read of IO (SEVEN !!!)

[roudoudou]

There are definitely some 4-clocks opcodes that sync GA with z80. But are there opcodes that desynchronize z80 from GA? And does the 40007 work exactly the same as the 40010?
The diagram from read IO is even more puzzling.
7-clocks cycle read of IO (SEVEN !!!)

instructions are always synchronised by the GA, starting with opcode fetch. Instruction duration (caused by previous instruction) won't change anything, except the opcode fetch will wait a sort of "previous instruction termination".

On Amstrad Plus you can have "true" additionnal waitstates which can really change I/O timings and slow down Z80, but it's predictable and you'd have to really want it to experience it

[angelcaio]

Ca synchronization with the CRTC 6845 influence the cycles of the Z80?

[McArti0]

GateArray force length cycles of Z80.

https://www.cpcwiki.eu/imgs/b/b4/Z80_CPC_Timings_cheat_sheet.20230709.pdf

[Bread80]

The Gate Array READY signal drives the Z80's /WAIT input. The Z80 only listens to /WAIT when it's making bus access. For instructions which don't use the bus on one or more M cycles some cycles those cycles won't be stretched.

An example of this is ADD HL,ss, which takes three M cycles, 11T states. The only bus access is the M1 on the first M cycles. The second and third cycles will not be stretched by the gate array. Instead the next instruction will be the one which gets stretched to get everything back into sync.

It is theoretically possibly for an instruction to skip enough cycles to execute an extra M cycle, but I rather doubt there are any instruction which can do so.