Started by arnoldemu, 21:56, 20 January 16
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Quote from: remax on 23:30, 20 January 16I did an acid test on my Amstrad (mine was clorhydric i think), and it melted down...What next ?
Quote from: remax on 17:35, 21 January 16nothing...
Quote from: TFM on 20:48, 21 January 16You could at least tell a joke...
Quote from: Bryce on 23:07, 21 January 16That was a joke??Bryce.
Quote from: Bryce on 23:18, 21 January 16The "Si Si entre entre" joke.Bryce.
Quote from: andycadley on 01:25, 22 January 16Very cool, I shall have to have a good dig through this and the Arnold release and do my best to find any quirks you've missed. ;-)
Quote from: arnoldemu on 21:56, 20 January 16Download the Arnold source (Unofficial Amstrad WWW Resource) and look in the test folder.
Quote from: Executioner on 23:45, 13 February 16I did, and there are none of the above mentioned tests in the current src zip file.
Quote from: arnoldemu on 12:52, 14 February 16Sorry. I've zipped it separately here:Unofficial Amstrad WWW Resource
Quote from: arnoldemu on 21:56, 20 January 16Accuracy is important in emulation.I present the tests I have written to test Arnold emulator and the devices it emulates. The "acid" test for CPCs.
Quote from: roudoudou on 10:24, 18 April 16I read some asic tests and they are quite simple. Really simple.
Quote from: roudoudou on 10:24, 18 April 16I'm currently coding an intro with Winape with an ASIC split each line EQ that means that i change 6801,6802,6803 & 6804 register every lines. As the splits are following a curve, i'm doing some computations and i can't change every registers in a short time. Registers changing is dispatched along the 64 nops i have for a line. I finally managed to set the timing FOR Winape. The code works, the intro is fine. But when i sent my code to a friend how own a real CPC+, everything goes wrong...
Quote from: roudoudou on 10:24, 18 April 16So i ask Offset/Futur's because his emulator seems to be the most advanced and accurate to give me some tips about the ASIC. Here is an extract of his very interresting answer:(original) Il y a plein de cas limites et d'artefacts. (...) les splits sprite hard qui sont décalés d'un ou deux pixels lorsqu'ils sont faits avec certains instructions du Z80 (...) lors de la HBL le CPC+ fait des tonnes de choses avec une séquence bien précise, et les timings dépendent des fonctionnalités activées... et de ce que font les DMA (un DMA en pause induira des timings Z80 différents d'un DMA en écriture de registre, etc..).(translation)There is many limit cases and artifacts / doing split with hardware sprite (change hardware sprites coordinates/size during the display of them for example) may occurs some pixel translation according to the Z80 instruction doin' the change / during the HBL, ASIC refresh his own registers in a specific order. Timings of ASIC management depends on features enabled... AND of what DMA are doing!!!!!! A paused DMA will cause differents timing than a DMA writing a register.
Quote from: arnoldemu on 15:51, 18 April 16Do these tests pass 100% on Ace?
Quote from: arnoldemu on 11:31, 18 April 16Arnold doesn't emulate that demo properly because it also needs exact instruction timing which arnold doesn't have.
Quote from: roudoudou on 23:33, 19 April 16when you say "exact instruction timing", you mean doing things (read/write) at the exact time, instead of executing the whole instruction and add total time of the instruction?
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