Author Topic: amstrad cpc "acid" test  (Read 24667 times)

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Offline andycadley

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Re: amstrad cpc "acid" test
« Reply #100 on: 21:13, 06 August 17 »
Looks like Kev has already updated the wiki but my tests seem to agree, accessing the sprite pixel data disables the sprite for the duration of the read/write. Accessing the position registers doesn't seem to have the same effect.

Offline arnoldemu

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Re: amstrad cpc "acid" test
« Reply #101 on: 21:36, 06 August 17 »
Looks like Kev has already updated the wiki but my tests seem to agree, accessing the sprite pixel data disables the sprite for the duration of the read/write. Accessing the position registers doesn't seem to have the same effect.
yeah it didn't take that long to test :)

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Offline andycadley

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Re: amstrad cpc "acid" test
« Reply #102 on: 22:32, 06 August 17 »

yeah it didn't take that long to test :)


yeah, a few quick and dirty tests demonstrates it. :-)

Offline arnoldemu

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Re: amstrad cpc "acid" test
« Reply #103 on: 10:54, 07 August 17 »

yeah, a few quick and dirty tests demonstrates it. :-)
It takes a bit longer to make a nice polished test that tries all of the possibilities in one screen, but that's what I'll do :)

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Offline roudoudou

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Re: amstrad cpc "acid" test
« Reply #104 on: 21:16, 07 August 17 »
I'm trying to do a cool SPLIT_ADR test cartridge but i think i have to work better on DMA cause i do not succeed in highlitghting the wait-state effect of DMA


Some capture to show you what it looks like now


But i can already tell:
- low byte of SPLIT_ADR & high byte of SPLIT_ADR are taken into account simultaneously
- Arnold is reading SPLIT_ADR 2 nops too late (the screen goes wrong 2 lines before the real CPC when the code has more NOPS before the register override)


Will work tomorrow on it  ;D


code extract
Code: [Select]


macro InnerSplit64
attente=15
repeat 16
ld e,(hl) : inc h : ld d,(hl) : inc h : ld a,c : ld (#6801),a : ld (#6802),de
defs attente+8,0
exx : ld (hl),b : exx ; <- Here is the register override
if attente>0
defs 15-attente,0
endif
; update counters
inc c : ld a,(hl) : inc l : dec h : dec h : ld (#6804),a ; the purpose is not to test the SSR
defs 64-31-15-8,0
attente=attente-1
rend
mend
use RASM, the best assembler ever made :p

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Offline ThomH

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Re: amstrad cpc "acid" test
« Reply #105 on: 06:03, 27 June 18 »
It depends on the drive. My 3.5" drive is very quick to go ready and not-ready (the test can't measure it).

My 3" drives are much slower and they are not all the same.

I'm a year late, but while having terrible difficulty trying to get good substantive detail on the FDC I stumbled upon this thread.

Almost certainly the 3" drives implement the traditional meaning of RDY: it goes active two index pulses after motor on. The assumption is that proper speed will have been reached by then. How long it takes you to get to two index pulses obviously depends on initial rotation position plus how long your drive motor actually takes to get up to speed.

IBM redefined it. With any drive intended for a PC, RDY is inactive when you insert a disk. It becomes active after the head has stepped. It remains active until the disk has been ejected. So it's no longer related to rotation speed at all, it's effectively a disk-has-changed indicator.
« Last Edit: 17:17, 27 June 18 by ThomH »

Offline roudoudou

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Re: amstrad cpc "acid" test
« Reply #106 on: 15:01, 08 November 19 »
Hey, i discussed with Offset about ACE emulator and testing AND sprites artefacts some people found
During the discussion, we were talking about splitrasters timing changes according to the instruction doing the change (see the previous pages of the topic)
Offset told me the time-shift between instructions used is always the same BUT there is another time-shift between functionnalities used in the ASIC
So i made a little (an incomplete test)
During sprite drawing, i'm changing X, then i'm changing zoom (to zero)
I noticed there is a little difference with changing X, then changing zoom to smaller width (i think it's the real end of the big sprite/2 width)
Then 4 lines doin nothing
Then changing X and changing Y position. This time we can see a very small and delicate line when switching back to full width
The CPR is not finished, i may change the visuals (for a moar visible evidence)
Juste some screens attached to this post


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Offline roudoudou

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Re: amstrad cpc "acid" test
« Reply #107 on: 15:06, 01 February 20 »
ouuuups, did not post the last cartridgethis side effect occurs also with read access to sprites...

use RASM, the best assembler ever made :p

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Offline roudoudou

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Re: amstrad cpc "acid" test
« Reply #108 on: 17:37, 11 May 20 »
Hi Folks! A new ACID test for emulators  :P
This one display all registers values at boot (i've red that Z80 must set SP and AF to 0xFFFF at reset but neither M4 nor C4CPC are able to do it!)
Also there is a visual demonstration of PSG concurrency access waitstates (3 DMA list + OUT to PSG at the "same" time)

use RASM, the best assembler ever made :p

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Offline gerald

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Re: amstrad cpc "acid" test
« Reply #109 on: 18:01, 11 May 20 »
i've red that Z80 must set SP and AF to 0xFFFF at reset but neither M4 nor C4CPC are able to do it!
Where did you read that  :o

From Z80 user manual
"Reset (input, active Low). RESET initializes the CPU as follows: it resets
the interrupt enable flip-flop, clears the PC and registers I and R, and sets
the interrupt status to Mode 0
. During reset time, the address and data bus
go to a high-impedance state, and all control output signals go to the
inactive state.
"

Offline roudoudou

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Re: amstrad cpc "acid" test
« Reply #110 on: 18:08, 11 May 20 »
Where did you read that  :o

From Z80 user manual
"Reset (input, active Low). RESET initializes the CPU as follows: it resets
the interrupt enable flip-flop, clears the PC and registers I and R, and sets
the interrupt status to Mode 0
. During reset time, the address and data bus
go to a high-impedance state, and all control output signals go to the
inactive state.
"
https://acpc.me/ACME/MATERIEL/COMPOSANTS/CIRCUITS_INTEGRES/Z80/Z80_The_Undocumented_Z80_Documented(2005)[ENG].pdf
This register init is not a big deal anyway

BUT now i checked a CPC at startup is in IM 0 mode in contrary of Winape (that's why many Winape programmers cannot run their programms on a real machine)

use RASM, the best assembler ever made :p

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Offline gerald

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Re: amstrad cpc "acid" test
« Reply #111 on: 19:25, 11 May 20 »
https://acpc.me/ACME/MATERIEL/COMPOSANTS/CIRCUITS_INTEGRES/Z80/Z80_The_Undocumented_Z80_Documented(2005)[ENG].pdf
This register init is not a big deal anyway

BUT now i checked a CPC at startup is in IM 0 mode in contrary of Winape (that's why many Winape programmers cannot run their programms on a real machine)
If needed, I can force AF and SP on start when loaded via CprSelect (of when cart image is bigger than 128k).
For direct load (card image smaller than 128k) SP will be modified due to the way the C4CPC make the Z80 wait : RST0. Side effect is also that RAM is filled with 0x0001 ;D
If you really need to have the Z80 in a true out of reset state is to first power the C4CPC via the USB port, then power the CPC.
Now to know if the SP and AF are really reset or they value is a side effect of the reset / powerup one would need to reverse engineer the Z80 layout. 
Set / Reset cost 2 NAND per register bit, and that's usually the reason to have set/reset on reset to the minimum.

Offline roudoudou

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Re: amstrad cpc "acid" test
« Reply #112 on: 19:28, 11 May 20 »
For direct load (card image smaller than 128k) SP will be modified due to the way the C4CPC make the Z80 wait : RST0. Side effect is also that RAM is filled with 0x0001 ;D
For most of my cartridges, i erase all the memory to be sure  ;D
use RASM, the best assembler ever made :p

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Offline roudoudou

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Re: amstrad cpc "acid" test
« Reply #113 on: 11:28, 12 May 20 »
new DMA test (still not complete)

use RASM, the best assembler ever made :p

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