Author Topic: Found why ReSeT 0 - Outer World Music work on CRTC0 and not on um6845r CRTC1 !  (Read 250 times)

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Offline megachur

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Quote
In this post : https://www.cpcwiki.eu/forum/emulators/cpcepower-v1804/msg165655/#msg165630
I found a bug for this demo "ReSeT 0 - Outer World Music" but I not found exactly why it affects some CRTCx other than the CRTC0 !
Remeber :
  The CPC 6128 CRTC 0 on which we hear the music has a PPI Toshiba TMP8255AP-5 (8804A), the cpu: Z8400APS Z80 CPU (8609)
  The CPC 6128 CRTC 1 on which the music is not heard (and meters remain at 0): PPI NEC D8253AC-5 (8609EJ), the cpu: Z0840004PSC Z80 CPU (8803)

Code: [Select]
   org # 9541   ld hl, # 96b9   ld of, # e6a6
  ld bc, # f400
  .l954a
  ld a, d
  out (#ff), a
  out (c), c
  ld b, d
  out (c), 0
  dec b
  outi
  ld a, e
  out (#ff), a
-> here is the bug found on CRTC1 (and may be others or not)

out (# A6FF), # A6
cpu.ADDRBUS = #a6ff

(cpu.ADDRBUS&0x4000) == 0x0000 --> Chip Select CRTC = execute ENABLE of CRTC!
(cpu.ADDRBUS&0x0100) == 0x0000  --> Address Register Select
(cpu.ADDRBUS&0x0200) == 0x0200 -->Read Status Register

on CRTC0 -> it does nothing, so CPU.DATABUS don't change == #a6 !
so ppi.enable got #a6 on latchPortC and enable register write value to be send to ay (BDIR=1 and BC1=0)
but on some CRTC, this send other data,
for example CRTC1.um6845r, it's sending to cpu.DATABUS this :

// b7 not used
// b6 - LPEN Register Full
// b5 - Vertical Blanking
// b4-b0 not used

so BDIR =0 and BC1 is 0 (most of the time) so there is no write to ay register value !


Please, if you can test this demo on your amstrad cpc, send result here with your type of CRTC : this will be possible to check next with a little program the result send by CRTC when trying to read "Read Status Register" value if exists !


Code: [Select]
  inc c
  ld a, # 0d
  cp c
  jr nz, l954a
  bit 7, (hl)
  jr nz, l956d
  ld a, d
  out (#ff), a
  out (c), c
  inc b
  ld a, e
  out (#ff), a
  outi
  .l956d
  ld b, d
  out (c), 0
  ret