Started by Executioner, 11:28, 27 November 09
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Quote from: Executioner on 11:28, 27 November 09After many years, I think I've finally worked it out properly! After looking at implementing an accurate emulation of the Z80 at the instruction sub-cycle level in order to get ZX memory contention timing working properly, I thought it would be nice to actually work out how the Z80 timing really gets adjusted by the CPC hardware, and I think I've finally worked it out. Seems to work by aligning memory read and write instructions to every fourth cycle. I've applied this to the full instruction set and it appears to work fine, except for the OUT (C),r instruction, so there's something weird going on with the timing there so the CPC may be modifying the OUT timing in another way, but it doesn't appear to affect OUT (n),A the same way.Did one of the CPC variants actually had the Gate Array implemented in logic? Does anyone actually have one or better still a circuit schematic or similar?
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