Due to my last failing around Z80 CPC Timing, I build the theorical CPC WAIT_n generator table based on plustest.dsk versus UM0080.pdf (z80 doc)
https://github.com/renaudhelias/CoreAmstrad/tree/master/LatencesCPC (https://github.com/renaudhelias/CoreAmstrad/tree/master/LatencesCPC)
And back in time I have already tested instruction timing one per one on this Z80 and they seems correct (without HALT/IO_ACK ... measures)
This result on that :
constant latences:LATENCE_ARRAY :=(
16 => '1', -- "10"
34 => '1', -- "22"
42 => '1', -- "2a"
192 => '1', -- "c0"
197 => '1', -- "c5"
199 => '1', -- "c7"
200 => '1', -- "c8"
207 => '1', -- "cf"
208 => '1', -- "d0"
213 => '1', -- "d5"
215 => '1', -- "d7"
216 => '1', -- "d8"
223 => '1', -- "df"
224 => '1', -- "e0"
227 => '1', -- "e3"
229 => '1', -- "e5"
231 => '1', -- "e7"
232 => '1', -- "e8"
239 => '1', -- "ef"
240 => '1', -- "f0"
245 => '1', -- "f5"
247 => '1', -- "f7"
248 => '1', -- "f8"
255 => '1', -- "ff"
-- "cb" NOT TESTED
-- "dd" NOT TESTED
-- "ed" NOT TESTED
-- "fd" NOT TESTED
others=>'0');
constant latences_CB:LATENCE_ARRAY :=(
...
First range of Z80 instructions is fully covered here, and is -currently for this experiment- being possibly simplified to being slown down each bad instruction by 2 clock edges.
So then when I run plustest.dsk instruction timing tesbench, I result on several bad timings :
( better render of this table at http://www.cpcwiki.eu/index.php/FPGAmstrad#Instruction_timing_:_talk_about_r005.8.16c29 (http://www.cpcwiki.eu/index.php/FPGAmstrad#Instruction_timing_:_talk_about_r005.8.16c29) ...)
Hex Inst CPC timing r005.8.16c29
32 LD (nn),A 4 3
3A LD A,(nn) 4 3
C0 RET NZ 2/4 2/3
C4 CALL NZ,nn 3/5 3/4
C5 PUSH BC 4 3
C7 RST 0H 4 3
C8 RET Z 4/2 3/2
CC CALL Z,nn 5/3 4/3
CD CALL nn 5 4
CF RST 8H 4 3
D0 RET NC 2/4 2/3
D4 CALL NC,nn 3/5 3/4
D5 PUSH DE 4 3
D7 RST 10H 4 3
D8 RET C 4/2 3/2
DC CALL C,nn 5/3 4/3
DF RST 18H 4 3
E0 RET PO 2/4 2/3
E3 EX (SP),HL 6 5
E4 CALL PO,nn 3/5 3/4
E5 PUSH HL 4 3
E7 RST 20H 4 3
E8 RET PE 4/2 3/2
EC CALL PE,nn 5/3 4/3
EF RST 28H 4 3
F0 RET P 2/4 2/3
F4 CALL P,nn 3/5 3/4
F5 PUSH AF 4 3
F7 RST 30H 4 3
F8 RET M 4/2 3/2
FC CALL M,nn 5/3 4/3
FF RST 38H 4 3
Most of them being about "jump" instruction except two of then (the two first one in this list).
Question : plustest.dsk timing instruction testbench is based of HALT/IO_ACK/NOP great implementation. Is there a luck about one of them not implemented correctly ? Is there several strategies around testing timing instruction on this plustest.dsk testbench ?