6128 - Help to test a 40010

[biishop]

Hi,

My CPC still not boot and I'm actually look after INT signal on the Z80 because it is completly flat. And according to the procedure I read this one should be pulsed.
I'm equiped with a DSO338 limited to 5Mhz. When I say pin6 pulse on Z80 I see a 4Mhz ocilliation.

Z80 CLK 4Mhz (tested on another CPC working well)

40010 VDD1&VDD2 are 4.50v
40010 CCLK 1Mhz
40010 INT is flat too
40010 READY also 1Mhz
40010 NRESET 4.5v
40010 CK16 4Mhz

I buy another 40010 and I'm front the same trouble (dont know if the new one work well).

For information this state appeared gradually after a few boot with a black box and a few periods of correct operation before completely losing the video output signal.

Is 1Mhz is normal on 40010/pin4 ?

And have you any simple first check to ensure correct functionnality of the 40010?

CC

[gerald]

40010 VDD1&VDD2 are 4.50v -> NOT GOOD
40010 CCLK 1Mhz -> OK,
40010 INT is flat too -> int will stay low as long as the Z80 did not acknowledge the interrupt. If the interrupt is disabled, it will stay low forever
40010 READY also 1Mhz -> OK
40010 NRESET 4.5v -> OK
40010 CK16 4Mhz -> CK16 is the 16MHz input of the Gate array. You cannot measure it with a 5MHz sampling scope. But with CCLK/READY toggling at 1MHz, this mean that 16MHz is likely OK

For information this state appeared gradually after a few boot with a black box and a few periods of correct operation before completely losing the video output signal.

Black box on screen is one of the main symptoms of dead RAM.
The fact the you only have 4.5V on the 40010 supplies instead of 5V hint that something is consuming too much on the board.
Check that none of the ram device is overheating (mind your finger)

[biishop]

I find this information, it mean 40010 compute INT output from HSync signal.


I will look in this direction. But if you have advice I am interested 

[biishop]

I've all ready turn arround ram chip and none of them seem to be so hot.
I've also change all chip from low bank for nothing and I test also the trick with the HAL16 and jumper to try to boot with high bank of ram chip without succes too.


I just redo a precise multimeter measurement this time (not with my rotten oscilloscope) and I have 5v exactly.

[gerald]

I find this information, it mean 40010 compute INT output from HSync signal.

Except that the description is partially false.
The INT signal goes low to trigger the interrupt and stays low as long as the Z80 does not execute an interrupt acknowledge cycle.
If interrupt is disabled, and it is out of reset, the int signal will stay low until the interrupt is enabled.
Enabling the interrupt is done in the FW after a set for initialisation.

So you should not focus on the interrupt signal 

[gerald]

I've all ready turn arround ram chip and none of them seem to be so hot.
I've also change all chip from low bank for nothing and I test also the trick with the HAL16 and jumper to try to boot with high bank of ram chip without succes too.


I just redo a precise multimeter measurement this time (not with my rotten oscilloscope) and I have 5v exactly.

Can you check the ROM ? Do you have an XMEM or equivalent to run an external FW ROM ?

[biishop]

Du CRTC:
VCC 5.0v
HSYNC Nothing
VSYNC Nothing
CLK 1Mhz
RESET 4.99v


Ok for INT, so that means something is locked in the boot sequence between Z80 and ROM execution?

For the rom I can unsold them, after I've a TL866 I will check if I can read it


Btw I've also 2 Winbond 27c512-45z

[biishop]

This is the 2 rom dump ...

[biishop]

Compare to cpcWiki Rom my 40051 and basic6128 (French AZERTY) are equivalent but my 40015 and os6128 (French AZERTY) are seriously different 

[biishop]

How it could happen is a wack thing 

Btw there is some readable text in the faulty Rom


There is really all our very dear Basic 1.1 in this so small space. I will never stop being so bothered by these things 

So actually I can't rewrite on this rom.

Can i rewrite on an original rom? --> No I cannot

I tell myself that if a bug could do it I should be able to get there.

I don't understand why Amstrad used 2x64K 128K roms, only one would have been enough for 2x64K. If I want to flash my 512K, I replicate the 64K 8 times? Otherwise what address should I have?

I think about that and it was so stupid ive just read some document about memory mapping

Where is the last 16K for D7, I read 6128 have a 3rd ROM bank (48K)?

My 40015 dump seem to be this one? --> For sure it is !

I know now, where it is. If i find it, I work a lot about that night !!
And all match perfectly with the reference


Sorry for all this stupid question and thank for your support.


I will come back to disturb you tomorrow, there it is late!

[gerald]

This is the 2 rom dump ...

The 40051 is a 32K ROM. It contains the FW on the lower 16K, and the BASIC on the upper 16K.
Can you re-dump it properly 

The 40015 is the AMSDOS ROM and is 16K only.

[biishop]

Hi Gerald,


I finish with this observation yesterday and after merging the 2 binary file from the zip from original 6128 low+basic and create a new 32K chip dump, they was unfortunately and exactly the same


I'm also equip with a little signal analyser and do you think i can use it to log opcode startup sequence of the Z80 to see if something is execute by the Z80 at the power up ?


It there somewhere a trigger to be sure low Rom is in use from 40010 ? Or this is only needed for high bank and for ram usage ?

[Bryce]

If HSync and VSync are showing nothing, then the CRTC is most likely dead.

Bryce.

[gerald]

If HSync and VSync are showing nothing, then the CRTC is most likely dead.

If the Z80 does not initialise the CRTC register, it will not output anything as all register are reset to 0.
So there is still a possibility that the CRTC is functional but not initialised.

If the ROM and the Z80 are OK, there is not much that would prevent the CRTC to be properly initialised. It's one of the first thing done by the FW, the setting loop start after the ~20th instruction executed.
In such situation, I would 1st use my memtest, which is only relying on external ROM. It would at least confirm a working CRTC/GA/Z80.
If it would not, I would go for a Z80 boot trace with a logic analyser.

[Bryce]

I thought the the CRTC produced a default H/VSync even if not initialised and all registers at 0?

Bryce.

[biishop]

Ok,


So I measured few thing around CRTC


CLK pulse 1Mhz and 1.35v with multimeter this value seem low no ?
VCC 5.00v
R/W not regular pulse 0.9MHz 2Mhz 1.35v
E is flat 0v or few mili
RS same as R/W
CS not regular pulse up to 5Mhz but with 0v or few mili
Cursor flat 30mV
Display Enable up 3.67v
Reset up 5V
VSYNC/HSYNC flat with few mili 30mV


I allready test another 6845 I buy last year and I got same result as this one.
I dont have any hardware to try a boot with an external rom.


I will try to log some op code signal from the boot sequence so

[biishop]

This my my boot log:

12Mhz / 1 Sec / D0-D6 + CLK (done with PulseView)

I have done a lot of log, they have allways the same form. D5 up before other.
It done with a Chinese gadget which does not seem to me at all reliable. I'm really going to decide to equip myself with weaker and more efficient devices. I realize that it's shit. I did not want to spend too much money but as I want to spend more and more time on it I will have to spend money.

Do you have material advice for a 2-channel oscilloscope and analyzer in the € 200-300 range which would seem technically correct?

Ask me for other log if needed, I'll give you all needed.

PS: During this capture a strange thing apear, the relay for the K7 reader wake up. One time per 5 sec the first time and really quickly the second time.

[Bryce]

If D5 is always high, then something is holding it high. You need to find out which component is doing this.

Bryce.

[biishop]

Yep, something look wrong with D5 but who send him the op code at this step?
It look like the period seem more and more quick.
Then all other op pin code are use, its look like repeat sequence for all of them.

Gate Array send memory pointer trought IC115 and the rom send the correspondente value to the CPU.
Is another IC have the execution pointer before CPU ? Gate Array ?

How is can check this pointer? Is there any document to explain boot sequence ?

Whats the job of the 8255? I will look after that