Building your own single ROM expansion pcb

[martin464]

Hi,
I found this website that gives a simple circuit for a single ROM expansion pcb
https://bmpc.github.io/bulding-an-amstrad-cpc-expansion-rom/

Thought I might have a go at it. I kind of need a really small one to fit inside the case, and only need 1 ROM
But I want to fully understand it first, and see if anyone has any comments

One problem is He doesn't mention why there is a resister or diode there, just curious why that is
Secondly he doesn't appear to describe how his latch is constructed, just put a square box
Also I see some NOT's in his schematic. Not sure what they might be or if they're just part of the logic already

Other than this it made sense
His hardcoding rom 15 wouldn't work for me on a 464, probably would have to change the address decoding there a bit

Maybe this is of use to someone else, how this stuff works seems quite interesting
 

[Interrupt]

I think the diode protects against multiple drivers on the ROMDISABLE line bypassing the address decoding logic. The resistor I guess is a pull-up resistor to support that but I'm too rusty with this stuff to definitely describe why it is there.

[eto]

The latch is probably made using the NOR gates. See here: https://circuitglobe.com/rs-flip-flop.html

[Bryce]

Hi Martin,
      the diode is there so that the internal ROMDIS doesn't effect the expansions logic. It's present on every circuit that needs to connect to the CPC ROMDIS circuit (ie: you'll find it on every ROMBoard circuit you can find out there). The resistor is there to ensure that the ROMDIS line is definitely set high on startup in case the 74HC12 is in an undetermined state when the 5V rail is rising at startup. Possibly overkill, the circuit would most likely work without it being there, but the creator followed best practice (or just copied what he found on other devices), which considering the price and effort of a single additional resistor is fully understandable.

Bryce.

[WacKEDmaN]

the latch "box" is how latches are represented on a schematic....its just a flipflop as eto mentioned.. can use either discrete logic or packaged chip...

the NOTs are just inverters...

[martin464]

Great thanks for the info much appreciated
I wonder why A15 is used here to control the ROMDIS. That confused me a bit
What is special about A15 here?

[Interrupt]

From the post...
"Whenever the operating system is using the Lower ROM (firmware), all other ROMS (including expansion ROMS) must be disabled. This is achieved by connecting both the Q output of the latch and the A15 line to another AND gate. The output of this AND will determine if our ROM is enabled by setting the CE pin LOW and also disable the internal CPC ROM by bringing the ROMDIS line LOW."

[martin464]

I see that, but why A15?

[Interrupt]

If I've understood it right A15 going low would signal that the read was in the lower half of the address space and therefore a  potential request for reading from the lower ROM. 

[eto]

I see that, but why A15?

From https://www.cpcwiki.eu/index.php/Connector:Expansion_port :

• /ROMEN (ROM Enable; Output from Gate-Array). When /ROMEN="0" a ROM read operation is active. This signal is generated by the Gate-Array. This signal will be "0" when:
  
  

  • A15=A14="0" and bit 2 of the Gate-Array ROM configuration register is set to 0, (lower ROM enable)
  • A15=A14="1" and bit 3 of the Gate-Array ROM configuration register is set to 0. (upper ROM enable)
  • A expansion device (e.g. a ROM-board) can use this signal to activate the selected ROM plugged into the device.

[martin464]

ah I get it now thanks guys, the ROMs are either in upper address C000, or at 0000 for the firmware so A15 is all you need to tell them apart

On a 464 you could easily decode ROM 7 as well
I'm rather tempted to make some of the logic using transistors instead of the chips, might have a go at that

[TotO]

ah I get it now thanks guys, the ROMs are either in upper address &C000, or at &0000 for the firmware so A15 is all you need to tell them apart

Not really. If A15=0 the ROM is located from &0000 to &7FFF. If A15=1 the ROM is located from &8000 to &FFFF. You require to decode A14 to know the four 16K areas.

00 = &0000
01 = &4000
10 = &8000
11 = &C000

About the Firmware location, it is 00 or 11, so you can use a XOR logic to detect that.

[eto]

Not really. If A15=0 the ROM is located from &0000 to &7FFF. If A15=1 the ROM is located from &8000 to &FFFF. You require to decode A14 to know the four 16K areas.

I think the idea of that circuit is: if ROMEN is active and A15 is high, it must be upper rom. if ROMEN is active and A15 is low it must be lower ROM. The circuit in the DDI, CPC 664 and 6128 for ROM 7 also ignore A14 completely.

In which case will firmware be at &c000?

[TotO]

I think the idea of that circuit is: if ROMEN is active and A15 is high, it must be upper rom. if ROMEN is active and A15 is low it must be lower ROM. The circuit in the DDI, CPC 664 and 6128 for ROM 7 also ignore A14 completely.

OK, I though about a ROM location, firmware or others.

[martin464]

i think because there's only 2 possible locations for rom, 0000 or C000, low or high
so A14 is not needed
none of this would be true when looking at ram banking, but when it comes to rom there's only 2 choices, and why A15 is all that's needed
the firmware is always at 0000, any other rom will always be at C000

[Bryce]

I'm rather tempted to make some of the logic using transistors instead of the chips, might have a go at that

Discrete AND gates can be created with just diodes and a resistor. In fact one of the AND gates on my MegaFlash was done that way.

Bryce.

[eto]

Discrete AND gates can be created with just diodes and a resistor. In fact one of the AND gates on my MegaFlash was done that way.

Was there a specific reason for this? Or were you just a single AND gate short? 

[TotO]

It is an elegant way to avoid using a circuit just for a gate.

[Bryce]

Discrete AND gates can be created with just diodes and a resistor. In fact one of the AND gates on my MegaFlash was done that way.

Was there a specific reason for this? Or were you just a single AND gate short?

Exactly that. I needed one more AND gate and it would have meant adding a quad AND gate chip with three unused gates. Which is not just a waste of gates, but also would have made the PCB bigger. I've done this on commercial products I've designed too, not just hobby projects.

Bryce.