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CPC6128 - expansion board address decoding

Started by Wawavoun, 12:46, 25 April 23

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McArti0

this mosquito has definitely been hit... :o

watch the current.

Think about the END signal.
CPC 6128, Whole 6128 and Only 6128, with .....
NewPAL v3 for use all 128kB RAM by CRTC as VRAM
TYPICAL :) TV Funai 22FL532/10 with VGA-RGB-in.

Wawavoun

#26
;D Okay I must admit...

if every switches are on I need 17 mA... For sure 10 k pullup will also do the job and then current is less than 8.5 mA.

I do this kind of thing only one time. It is not for mass production.
If a problem appear I have to redo everything, pcb, soldering, etc...
For prototype it is more efficient to have flexibility even with a little bit higher price.

Regards.
Philippe
If you think adventure is dangerous try routine, you'll see it's deadly!

McArti0

2x LS688 = 40-65mA x 2  for nothing  :P
CPC 6128, Whole 6128 and Only 6128, with .....
NewPAL v3 for use all 128kB RAM by CRTC as VRAM
TYPICAL :) TV Funai 22FL532/10 with VGA-RGB-in.

Rabs

Quote from: Rabs on 21:03, 26 April 23So just bear in mind, I am new to this and these are my first boards, so quite happy for someone to suggest a better approach.

This is what I have assumed, taken from "The Ins and Outs of the Amstrad" book.

A15 low is the Gate Array
A14 low is the CRT
A13 low is the Expansion ROM
A12 low is the printer
A11 low is the PPI
A10 low is the expansion bus*
A7  low is the disk controller
A6  low is a reserved function
A5  low is a communication channel

F8FF also has special meaning, calling all expansion devices to reset.

So the addresses available are;
F8E0 - F8FE
F9E0 - F9FF
FAE0 - FAFF
FBE0 - FBFF

I use a pair of 74138s and some logic gates to select the correct address. One 74138 for the high byte address and one for the low byte. There are probably better ways but I have a lot of 74138s. I also created a pair of excel sheets to model the outputs from the 74138s (you can have these if you want them).

I use the logic NAND gates to ensure that A15-A12 are high and connect this to G2A and G2B on one of 74138s. I then connect A11 to G1, so A15-A11 must be high. I then use the outputs from the 74138 where A10 is low (F8 to FB).

I repeat a similar process with the with the low byte but only select those outputs from the 74138 where A7-A5 are high (selecting E0 or F0). I then combined the outputs from the two 74138s.

Hope this makes sense and hope in works? I should find out in a couple of weeks when the PCBs arrive, although limited testing on a prototype seems ok.

You cannot view this attachment.You cannot view this attachment.

So my PCBs have arrived  :) but the observant may have noticed the low address lines (A0-A7) connected to the 74138 did not match my excel model sheet and because I am not that observant I did not notice :picard:. So the addressing was not quite as I expected  :-X Anyway I have corrected this and new PCBs are on order.

 You cannot view this attachment.

So now waiting for corrected set of PCBs, to see if this works.

But the ones I have are not going to waste as they work with my home brew Z80 Computer which does not have the same sort of addressing restrictions as the CPC  :D

GUNHED

In the CPC Wiki there is an list of already used I/O addresses. It's also nice to see that there is actually more 'space' than expected. 

For new developments please do use a fully decoded design (address IO) to stay compatible (as much as possible) to already existing hardware.  :) :) :)
http://futureos.de --> Get the revolutionary FutureOS (Update: 2023.11.30)
http://futureos.cpc-live.com/files/LambdaSpeak_RSX_by_TFM.zip --> Get the RSX-ROM for LambdaSpeak :-) (Updated: 2021.12.26)

Wawavoun

Hello,

On my CPC6128 I try this schematic connected on the expansion bus :


You cannot view this attachment.

I set the dip switches for decoding &FBFF or &FBFE, because A0 is not involved into the address decoding.

On the msb part of the address bus the LS688 correctly detect &FB so I can use his output (pin 19) down pulse as sync on the scope.

On the lsb part I see inconsistent bits at this moment (I assume A1 to A7 should be high when &FB on A8-A15)... Some are low during this pulse so of course the full address is not detected.

The problem is the same if I do a OUT &FBFF,&xx or a POKE(&FBFF,&xx).

The lsb address LS688 is working because with the scope in free run mode he is able to detect sometime &FF. I cross the LS688 but this is not the problem.

So I dont understand why I cant see at the same time &FB on the msb address and &FF on the lsb address.

I double check wiring etc... and didnt found the problem.

The CPC is working well and I already use the expansion port for other purpose (Usifac) without problem.

I am lost. Any help and advice's appreciated !

Regards.
Philippe 
If you think adventure is dangerous try routine, you'll see it's deadly!

McArti0

#31
Your circuit on outputs no. 19 does not take into account IOR IOW signals, so on the oscilloscope you also see the addresses of the currently executing program. These are also BASIC ROM addresses &C000-&FFFF
CPC 6128, Whole 6128 and Only 6128, with .....
NewPAL v3 for use all 128kB RAM by CRTC as VRAM
TYPICAL :) TV Funai 22FL532/10 with VGA-RGB-in.

Wawavoun

Thanks for the explanation.

Thinking to something similar (the $FBxx detected correspond to something different that the instruction I give) I have increase the record length of the scope (to may be 200 µs) but dont see other pulse after. 

I will do
- a measure using the expansion bus ioreq signal
- a measure at the output of the OR function so even if the requested address come later that the first $FBxx I should catch him.

Philippe

If you think adventure is dangerous try routine, you'll see it's deadly!

Wawavoun

The address decoding works !

Measurement problem... :doh:

But now I have to go deeper into the timing and do a small modification of the /WAIT signal management.
If you think adventure is dangerous try routine, you'll see it's deadly!

McArti0

CPC 6128, Whole 6128 and Only 6128, with .....
NewPAL v3 for use all 128kB RAM by CRTC as VRAM
TYPICAL :) TV Funai 22FL532/10 with VGA-RGB-in.

Wawavoun

At this point two things remain to solve I think :
1_ The AM9511 / Intel C8231 need that /CS stay low longer (at least 25ns) that /WR otherwise the data are not read correctly by the chip.
I should find a way to do that easily but dont know how ? Add a monostable ? Try something with a resistor + diode and capacitor ?
2_ The fpu /PAUSE signal is connected directly to the /WAIT line of the CPC. This is a problem because this line is shared with others and should be managed by open collector or something like that. I will try a serial 1N4148 so if /PAUSE is high the line can do what other peripherals want but is forced to low if /PAUSE is low.

Philippe
If you think adventure is dangerous try routine, you'll see it's deadly!

eto

Quote from: Wawavoun on 07:21, 01 June 231_ The AM9511 / Intel C8231 need that /CS stay low longer (at least 25ns) that /WR otherwise the data are not read correctly by the chip.
I should find a way to do that easily but dont know how ? Add a monostable ? Try something with a resistor + diode and capacitor ?
Following... I am curious how that can be achieved. I have a similar issue where (I think) a low signal is too short. 

Rabs

Quote from: Rabs on 18:06, 16 May 23
Quote from: Rabs on 21:03, 26 April 23So just bear in mind, I am new to this and these are my first boards, so quite happy for someone to suggest a better approach.

This is what I have assumed, taken from "The Ins and Outs of the Amstrad" book.

A15 low is the Gate Array
A14 low is the CRT
A13 low is the Expansion ROM
A12 low is the printer
A11 low is the PPI
A10 low is the expansion bus*
A7  low is the disk controller
A6  low is a reserved function
A5  low is a communication channel

F8FF also has special meaning, calling all expansion devices to reset.

So the addresses available are;
F8E0 - F8FE
F9E0 - F9FF
FAE0 - FAFF
FBE0 - FBFF

I use a pair of 74138s and some logic gates to select the correct address. One 74138 for the high byte address and one for the low byte. There are probably better ways but I have a lot of 74138s. I also created a pair of excel sheets to model the outputs from the 74138s (you can have these if you want them).

I use the logic NAND gates to ensure that A15-A12 are high and connect this to G2A and G2B on one of 74138s. I then connect A11 to G1, so A15-A11 must be high. I then use the outputs from the 74138 where A10 is low (F8 to FB).

I repeat a similar process with the with the low byte but only select those outputs from the 74138 where A7-A5 are high (selecting E0 or F0). I then combined the outputs from the two 74138s.

Hope this makes sense and hope in works? I should find out in a couple of weeks when the PCBs arrive, although limited testing on a prototype seems ok.

LB_CS.JPGHB_CS.JPG

So my PCBs have arrived  :) but the observant may have noticed the low address lines (A0-A7) connected to the 74138 did not match my excel model sheet and because I am not that observant I did not notice :picard:. So the addressing was not quite as I expected  :-X Anyway I have corrected this and new PCBs are on order.

 RABS664 Z80 PIO SCH 1.4.jpg

So now waiting for corrected set of PCBs, to see if this works.

But the ones I have are not going to waste as they work with my home brew Z80 Computer which does not have the same sort of addressing restrictions as the CPC  :D
New Boards have arrived and all working.

Wawavoun

#38
Hello,

Today my schematic is like that :


You cannot view this attachment.

The circuit did not work and I dont know why...
The basic test is to send &1A command (push pi on the stack) then read 4 times the stack and check if the 4 received bytes represent pi in floating format.

During the trials clock was 4 MHz, J3 and J4 in 1-2 position, J1 left open (I dont want generate interrupt at this moment). I use a 8231 instead of a 9511 but try both and see the same problem. Problem and signals are the same if I left J3 open.


What I can say is that :
- address decoding works (but /CS goes low during 1,7 µs which is long I think, Z80 manual say 4 clock cycles for io access then this is only 1 µs)
- A0 is ok : command/status to &FBFF and data in/out to &FBFE.
- LS139 works : /WR, /RD are consistent with /CS and /IOREQ (/WR is 125 ns shorter than /CS)
- clock is okay (the 8231 work asynchronously so his clock is not directly related with the bus timing)
- the data at Dx pins of the 8231 look correct during /WR or /RD low
- the 8231 react during read cycle (/PAUSE goes low)... I have test the chip on another computer and they work well.


I try to find a way to check if the problem come from command write or from data read operation.

May be the problem is somewhere in the timing but compare with the above schematics around the 8255 I dont see any functional difference...

Also reset the 8231 need at least 5 clock cycles. Remain the CPC clock active during reset ?

Thanks for any advice and help.
Regards.
Philippe
If you think adventure is dangerous try routine, you'll see it's deadly!

McArti0

#39
Am9511A       is CLK=2MHz
Am9511A-1    is CLK=3MHz

The 8231 could run at up to 3 MHz
and the 8231A and 8232 up to 4 MHz (a slight improvement on the Am9512 which was limited to 3 MHz)

Do You have 8231A ?  ??

Am9511A-4DC   is CLK 4MHz
CPC 6128, Whole 6128 and Only 6128, with .....
NewPAL v3 for use all 128kB RAM by CRTC as VRAM
TYPICAL :) TV Funai 22FL532/10 with VGA-RGB-in.

Wawavoun

Yes.

And I test it at 4 Mhz on the other computer.
If you think adventure is dangerous try routine, you'll see it's deadly!

McArti0

#41
If you have 4MHz version then you set J2-(3-4).

at 2MHz all timiing is too slow for CPC.
CPC 6128, Whole 6128 and Only 6128, with .....
NewPAL v3 for use all 128kB RAM by CRTC as VRAM
TYPICAL :) TV Funai 22FL532/10 with VGA-RGB-in.

Rabs

I have not fully read this myself just skimmed it but may be of interest AM9511 Arithmetic Processor.

Rabs


Animalgril987

Quote from: Rabs on 12:08, 02 June 23I have not fully read this myself just skimmed it but may be of interest AM9511 Arithmetic Processor.
@Wawavoun The article that @Rabs provided a link for ( above) suggests connecting the FPU chip select pin to ground, and using the decoded address to gate /WR and /RD to the FPU. This way, the FPU is always selected, but only responds when it's ready or write pins are selected by the address decoder.
The author used this method to interface one to his CP/M machine.

Rabs

Quote from: Animalgril987 on 13:08, 02 June 23
Quote from: Rabs on 12:08, 02 June 23I have not fully read this myself just skimmed it but may be of interest AM9511 Arithmetic Processor.
@Wawavoun The article that @Rabs provided a link for ( above) suggests connecting the FPU chip select pin to ground, and using the decoded address to gate /WR and /RD to the FPU. This way, the FPU is always selected, but only responds when it's ready or write pins are selected by the address decoder.
The author used this method to interface one to his CP/M machine.
Also not sure how you can use WAIT given its assertion by the Gate Array and timing with CRTC.

Animalgril987

#46
@Rabs I believe the GA output to the Z80 /WAIT is open collector, so an open collector buffer between fpu /PAUSE and cpu /WAIT should suffice ? ( I assume ( yeah, I know: NEVER assume!) that CPC has a pull-up resistor on /WAIT)
Or it might need the timing circuit shown on page 16 of the interface guide you linked to ( the OR gate will probably have to be open collector output ).

Animalgril987

#47
Better yet: page 18 has a Z80 interface. But, as before, an open collector buffer will be needed in the CPC case.
And don't include the connection from fpu END to Z80 INT.

McArti0

That signal on expansion port is not WAIT INPUT. This is READY OUTPUT. and have R=82 Ohm.
CPC 6128, Whole 6128 and Only 6128, with .....
NewPAL v3 for use all 128kB RAM by CRTC as VRAM
TYPICAL :) TV Funai 22FL532/10 with VGA-RGB-in.

Animalgril987

Oops! Yes. Good point.
So: modify the interface to use a 3rd address, and read /PAUSE from a latch, looping until /PAUSE goes high?

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