I don't understand access to internal RAM

[Canou1967]

Hi,

the address bus and the CRT address the RAM via the 74LS153 but I don't understand the distribution of the signals.
I made a table below.
  

/CPU	/CASAD	RAM-A7	RAM-A6	RAM-A5	RAM-A4	RAM-A3	RAM-A2	RAM-A1	RAM-A0
L	L	A14 OUT	A15 OUT	A12	A13	A10	A11	A0	A9
L	H	A7	A8	A5	A6	A3	A4	A1	A2
H	L	CRTC.MA12	CRTC.MA13	CRTC.RA1	CRTC.RA2	CRTC.RA3	CRTC.RA0	/CCLK	CRTC.MA8
H	H	CRTC.MA6	CRTC.MA7	CRTC.MA4	CRTC.MA5	CRTC.MA2	CRTC.MA3	CRTC.MA0	CRTC.MA1

Address RAM work in Rows Columns address or in page mode in ROW, Column, Column.
I don't understand order of address and mixing mode in MSB and LSB address.
Can you help me?
Regards
Canou  

[eto]

This blog explains everything in great detail. I can highly recommend it:

https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/

[Canou1967]

great Yes but no answers on this

[McArti0]

Remember that the nominal address names in the RAM chip have no significance, because every RAM cell is the same. This is not ROM. It only has a minor significance in the order in which DRAM is refreshed.

/CPU	/CASAD	RAM-A7	RAM-A6	RAM-A5	RAM-A4	RAM-A3	RAM-A2	RAM-A1	RAM-A0
L	L	A14 OUT	A15 OUT	A12	A13	A10	A11	A0	A9
L	H	A7	A8	A5	A6	A3	A4	A1	A2
H	L	CRTC.MA12	CRTC.MA13	CRTC.RA1	CRTC.RA2	CRTC.MA9	CRTC.RA0	/CCLK	CRTC.MA8
H	H	CRTC.MA6	CRTC.MA7	CRTC.MA4	CRTC.MA5	CRTC.MA2	CRTC.MA3	CRTC.MA0	CRTC.MA1

[Canou1967]

yes thank you it's something that I had anticipated but what disturbs me is A0 and A8 which are reversed between MSB and LSB bytes.

especially for page mod of RAM. but maybe not used in CPC...

[McArti0]

It is important that, for example,
A15-OUT is paired with CRTC.MA13
A14-OUT is paired with CRTC.MA12
CRTC.RA1 is paired with A12
CRTC.RA2 is paired with A13
CRTC.MA9 is paired with A10
CRTC.RA0 is paired with A11
A0 is paired with /CCLK

because this creates the screen structure in memory.

[Canou1967]

This is why the use of page read is not possible on CPC. Thank you all for these answers, I understand better.

[McArti0]

disturbs me is A0 and A8 which are reversed between MSB and LSB

the A0 - /CCLK pair must be in CAS because CCLK is changed in two consecutive CAS when reading two bytes of screen memory in the RAS-CAS-CAS sequence.

A8 has a pair of CRTC.MA7. nothing special

[Bread80]

Also, the CRTC addresses are used for DRAM refresh, which happens during RAS cycles. The design needs to ensure that every one of the 256 rows get regularly cycled. The best way to do ensure that is to use the low bits of the address. As McArti0 mentioned CCLK is driving the A0 on the double CAS cycles so needs to be on the CAS side, which is why it's swapped. The remainder is probably just convenience for PCB routing.

[Canou1967]

thank you