crtc settings which cause ram refresh to stop

[arnoldemu]

It was mentioned to me (by NWC I think) before that if the displayed screen width or height was set to 0 for a long time then ram refresh on the cpc would stop.

I believe this is genuine but I never saw it. I'm not sure the reason was ever worked out?

I have re-read the mc6845 pdf and noticed this on one of the timing charts:

"The present CRTC freezes MA addresses at Nvd*Nhd during vertical retrace. A design change is pending to allow MA to free run during vertical retrace time".

In the document vertical retrace is from VCC=R6 to VCC=R4. In other words the upper and lower border. Horizontal retrace is from HCC=R1 to HCC=R0. (the left and right border)

So this means that if you set R6=0 then refresh would be impacted for the entire frame (MA would be stuck on a single value), whereas setting R1=0 then refresh would be like normal. Of course to see the ram contents go you would also need to have code that didn't read from ram, so something like a DI:HALT would probably do it.

Has anyone else heard about this?

I think it is a MC6845 only problem.

(Plus appears to have a ram refresh problem but I don't think it's caused by the same mechanism as this, I think that one is caused by the wiring of the RAM).

[PulkoMandy]

On the CPC, both the z80 and the CRTC are refreshing the RAM. So, to get into this problem, you would have to both disable the CRTC display, or put it in a mode where it always accesses the same address(es), AND also disable the z80 refresh, for example by repeatedly writing the same value to the R register. You have to be quite unlucky to trigger all of this at once by accident  .

[gerald]

AND also disable the z80 refresh, for example by repeatedly writing the same value to the R register. You have to be quite unlucky to trigger all of this at once by accident  .

You don't need to do that, the refresh cycle of the Z80 never reach the DRAM. Only R/W access to memory is done, the refresh cycle is ignored : the GA is fetching the video RAM at that time.

[arnoldemu]

You don't need to do that, the refresh cycle of the Z80 never reach the DRAM. Only R/W access to memory is done, the refresh cycle is ignored : the GA is fetching the video RAM at that time.

Yes.

I'm going to test my theory on my CRTC type 2 this weekend.

I will setup a picture, use R6=0, wait a short time and then display the picture.

My theory is that the data will degrade in parts of the RAM and the displayed picture will become corrupted in some way.

[arnoldemu]

On the CPC, both the z80 and the CRTC are refreshing the RAM. So, to get into this problem, you would have to both disable the CRTC display, or put it in a mode where it always accesses the same address(es), AND also disable the z80 refresh, for example by repeatedly writing the same value to the R register. You have to be quite unlucky to trigger all of this at once by accident  .

I can force the CRTC (type 2) to access the same address by setting R6=0 I believe if the documentation is accurate.
I will put my test code in a fixed location and a tight loop so that few address lines are refreshed when it is executed.




So, a question for @gerald: If I wanted to block the disptmg output from the crtc so that border is not displayed by the GA and I can then see the MA address during border what do you suggest is the best way for me to do this? I want to be able to reverse the change.

[gerald]

I can force the CRTC (type 2) to access the same address by setting R6=0 I believe if the documentation is accurate.
I will put my test code in a fixed location and a tight loop so that few address lines are refreshed when it is executed.




So, a question for @gerald: If I wanted to block the disptmg output from the crtc so that border is not displayed by the GA and I can then see the MA address during border what do you suggest is the best way for me to do this? I want to be able to reverse the change.

You may disconnect the DISPLEN pin at gate array level. Extract it from socket, slightly bend the pin (9 on 40010) so it will not go in the socket anymore, and put the gate array back in the socket. But there is a risk of breaking the pin.
I expect the unconnected pin to naturally go to high level (ttl input), so the display will be always enabled. If not, and you will see it by having nothing on the screen, you will have to add a pullup to the pin.