Designing a CPLD replacement for the GateArray

[SerErris]

Hi, starting from the fantastic GateArray decapping thread, I am going to design a CPLD replacement.


I am still figuring out some stuff, but I will report here and ask questions and would appreciate any feedback and recommendations.


So current plan is the following.

Using an Intel MAX V 128 LEs gives me enough gates to fully implement the GAs.


I am choosing Intel as I alread do have the development environment available because of FPGA stuff.

5M160ZE64C5N is about 3,68€ if I buy a single one, which sounds absolutely reasonable for the project.

For the level conversion I am looking at those devices (TTL to LVTTL) CY74FCT2827T which are 10 bit Buffers ... I originally thought I would need to convert any input, but learning now, that many PINs are actually pulled up in the gate array. So they would not require any conversion, as high is just what they gate array pulls them up to.

Inputs with Pullups:
WREQ
M1
RD
IORQ

Output with Pullups:
Ready
PHI (Z80 clock) (passive pull up? What does that mean?)
Interrupt

All the rest of the output input and output lines looks like driven by someone to high or low (e.g. RAM is driving to high and low).

Please correct anything I got wrong here.

Now some direct questions regards CPLD:

If I have an input Pullup ? Is there anything I need to select on the input?

Would I need to pull them up externally? I cannot see any pullup (or choices) on the MAX V.

[Bryce]

Hi,
are you aware that @gerald has a CPLD (or it may be an FPGA) replacement design already finished?

Bryce.

[SerErris]

No I am not. All my googeling has not shown anything.

So we do already have a complete solution (PCB, programmable device, BOM + the code?)

I am aware of the code, but not aware there is anything ready to get produced.


Do you have a link ... if that is obsolete work, than I would stop it.

[SerErris]

The only thing I found is this here:
https://forum.system-cfg.com/viewtopic.php?t=11695

But that is neither ready yet, nor is it public (you build or buy it).

[Bryce]

https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/a-minimal-gate-array/msg198585/#msg198585

Not yet public, but completed.

Bryce.

[gerald]

Not public yet and due to the current component sourcing mess I can't make some for beta testing  In the mean time, I am thinking of a way to update it from the CPC itself, in case of bug or future added features 

[SerErris]

Ah okay ...


I do look at something like that now ..


ATF1504AS-7AX100

This is compatible with the old Altera EPM7064 and with 100 PINs has enough pins to have both - the normal logic and the JTAG programmer port available.


That should be a very cheap solution as you only need the CPLD on a carrier PCB for the DIP 40 PIN slot.


And you can programm it with JTAG even within the device if you have some JTAG programmer ...


Logic to program it from inside the CPC is too dangerous, because reprogramming the gate array within a running CPC is a little bit strange as you for instance will loss RAM access and other during the procedure. So you would need to put another microprocessor on the board and run a JTAG programmer in it (like an ESP or something alike). Not saying it is not possible, but maybe a little bit overloaded for just an FPGA. The only benefit would be, that you can change from 40007 to 40010 so USB port plus ESP + CPLD would form a "onsite" programmable item. But also not that cheap anymore.

[Shining]

I would opt for a relatively cheap solution. The Altera is a 5V type and seems available.

[GUNHED]

Well, if you redo the Gate Array, then it would be cool to have a 8 MHz version, so we can speed up the CPC.
One of mine runs well with 6 MHz, but it can't make it at 8 MHz because of the GA limitations.
Just imagine the awesome GFX. MODE 0 colors with MODE 1 pixel (ok, need 32 KB V-RAM, but that's fine). 

[SerErris]

That is a very simple option within the GA .. however something for a potential future feature list.


Goal 1:
Create a cheap solution, that plugs into the original slot and can be update by the user (JTAG required).


With the ATF150x chip I can do the whole setup with a single chip.


The 100 pin variant will also allow to have a jtag header on the PCB as well, so that it can be programmed in place (not within the CPC).

I have one question on timing ...
What gate propagation delay does the 40007 or 40010 have? Is that in anyway critical?

I mean for the 16mhz clock that would be a 62ns cycle time where 20ns is quite a large shift in the phase (30% actually) ..

However at 4mhz that is then not that relevant anymore ...

So if anyone know the propagation delay of the original gate arrays that would help to identify the correct speed for the CPLDs.

Ser

[SerErris]

Okay, after checking that the chip is actually big enough to fit the design I decided for now for this the Atmel chip as it simplifies the design.


Unfortunately the only available option is the 7ns option for the 100 QFP package ... but it now has just two components. I could potentially fit a Powerselector Jumper, so you could program it inside the CPC without the need to pull it out of the CPC. You would just need to switch a jumper and then have it powered from JTAT.


For now not implemented yet.

Attached are some screenshots of the PCB design:

[SerErris]

Ist evtl. das falsche Forum, aber kennt jemand einen KiCat Footprint für das Teil hier?

Habe das nicht gefunden und weiß auch nicht so recht wie ich danach suchen soll ..

[Bread80]

Your issue with generating a faster CPU speed is going to be the RAM timings. I've done some back-of-the-envelope calculations and there's not a lot of spare time within each GA cycle to speed things up.

[SerErris]

Yeah and you can not just pump up the clock to the gate array, as then video timings will be wrong. So it will be a lot of thinking involved to get it right.

But that discussion is maybe worth another thread focussing on it. If this idea has matured and such... I am happy to implemnt it in the CPLD if it fits into the module.


Thanks
Ser

[Fessor]

Well, if you redo the Gate Array, then it would be cool to have a 8 MHz version, so we can speed up the CPC.
One of mine runs well with 6 MHz, but it can't make it at 8 MHz because of the GA limitations.
Just imagine the awesome GFX. MODE 0 colors with MODE 1 pixel (ok, need 32 KB V-RAM, but that's fine). 

I see something like a crippled Atari ST powered by a Z80 with a palette of only 27 colors. And the ST itself suffered from a lack of hardware scrolling.

Perhaps an emulator programmer can extend their emulator and emulate an 8Mhz CPC with 32k VRam and Resolutions of 320x200x16, 640x200x4, 640x400x2 to see how that works out.

[SerErris]

Hmmm... looking at some other CPLD designs (not related to the CPC) I see a lot of small buffer caps on the vcc line. Do you think I do need to include some into the design? I do have plenty of space on the bottom side, where the 5V lines run and it is very easy to connect the lines with a small cap to ground. It is just more parts.

[SerErris]

It looks like I did a huge mistake :-(


The size of the socket I used is actually a 1" socket and as far as I remember the GA is the same size as the Z80 and that sits in a 0.6" wide DIP-40 package ...


This is a big issue as the chip is to big for the DIP-40 0.6" slot ...


Okay late today, will work on that tomorrow...

[SerErris]

Okay, I am back to Xilinx for now with this chip:


XC9572XL-10VQG64C

This is available in large quantities even today.


Now I need to figure out, if and what I need to do with the video outputs, which are the only ones that might be critical in terms of voltage ...

However I do not understand how the 50% signals are generated from a single digital output pin. @gerald  can you give me some insights on this?

[SerErris]

Okay I think I did understand the logic on the color output.


The output is actually a threestate output and 50% it means it is kept floating 0 is 0 and 1 is 100%. The external pullup is doing the rest. Sometimes it is really good to look at the schematics + the hardware :-)

Can someone confirm, that this is correct?

[gerald]

XC9572XL-10VQG64C

Too small 
The ink/border registers already require 17*5 bit = 85 DFF. You only have 72.

My first prototype used a XC2C256.

[gerald]

Can someone confirm, that this is correct?

Confirmed.

[SerErris]

And the next issue is - the package is to large ...


This is really painful .. Finding something that can actually get delivered .. and get programmed without cost for the design software and is at best 5V tolerant on the input ... ARGL.

[Shining]

I'm keeping my fingers crossed....

[issalig]

How many pins do you need?
Also take into account that ATF150XAS are compatible with EPM7XXXSLC and that can be programmed with a 3$ USB Blaster
Those EPMs can be found in aliexpress as "NEW (from dumpster)"  .

[SerErris]

Yep, they are all to large.


If there would be a 68 Pin TQFP Package that would be great, but the size (#of MacroBlocks) from Atmel/Microchip required just comes in a TQFP 100 package with a size of 14mm x 14 mm. That does barely fit between the pins and you cannot fit the connectors and the connection leads on the PCB anymore.

We need 35 free assignable pins + the 4 JTAG pins. Depending on the CPLD you also need e additional pins to reproduce the three color outputs.

I am now trying the 5M160Z from intel. That is the MAX V series and still in production. On the downside I need to implement voltage converters for the inputs (20 pins).

The plan is to use simple LVC 8bit transceivers, that will do the down conversion. For the output I do only need to take care of the RGB outs, which I will do with a quad 3-state buffer in normal TTL configuration.

But I do need two LDO voltage regulators, one for the cpld core voltage 1.8V and one for the the CCio 3.3V

The benefit on the intel chip: it does support 68 pin tqfp and will fit on the small PCB.

But I am asking to this round: would you be okay with a overlapping pcb that has the space for the CPLD on the side of the actual socket?

This variant could be build on a ADF1508 and would make the setup much easier. No LDO and potentially I also can remove the output buffers, because the ADF1508 could directly drive it.

I can post a picture tomorrow on my thoughts.

Benefit of the solution is:
1. Cheap
2. Simple - just one component.
3. Easy to maintain.

Downsides:
Relies on old technology
The PCB will hang over to one side to allow for enough space to fit the CPLD.



/Edit: Cleanup - typed it yesterday on my iPhone ..