Release of Amstrad Cpc Crtc Compendium (and Amazing Demo Rev 2021)

[lmimmfn]

What is this project you are currently working on regarding Vortex?

I do need to reverse envineer the ROM that is actually scrambled utilizing the M1 line. So depending on the M1 cycle it does scramble (actually descramble) or does not descramble the ROM. So if you read the ROM just normally (dump it, or read it with CPC) you will get all databytes scrambled and it is unusable.

I like to preserve it and get the unscrambled version (and commented source code).

So the way I now try to fill the remaining holes is, to sniff all rom reads with a Raspberry Pi PICO.

I have worked the last weekend on the code, which now looks ready (it does what I want it to do), and I can now hook up a CPC to this thing and start sniffing.

If you are interested in more detail, I could explain it, but probably not in this thread :-)

I'm not sure I understand, no ROM on 8bit or 16bit computers are encrypted or scrambled? (well not that I heard of from C64, Amstrad, Speccy, Amiga or Atari ST).
A dump of the CPC ROM should be directly executable via calls to same, i.e. can take hex from ROM and directky decompile without issue, unless I'm misunderstanding what you say?

[McArti0]

@lmimmfn
During M1, on which clock edge would you grab data from the data line on the first one, on the second one, or on another one?
On which clock edge would you retrieve data when Z80 reading from IO?
Will these be the same edge numbers if GA adds a WAIT signal?
These are detailed dilemmas.

[Longshot]

A cycle M consists of several T cycles, one of which has the particularity of taking into account the signal sent to the /WAIT pin by an external component. This wait cycle is commonly named Tw. At this Tw cycle it honors an active low signal on /WAIT and runs wait cycles until this line getting up again.

V1.8 updated. Thanks

Last version updated available here :
https://shaker.logonsystem.eu/

[McArti0]

"Note that bit 14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0, 1,
2. It can be at 0 or 1 on CRTCs 3 and 4. For compatibility reasons, it is strongly advised to always
set bit 14 to 1 to select PAL."

I recently discovered a trick
LD BC,#BC0F
OUT (C),C
LD A,#C7
LD BC,#3DFF
OUT (C),A.  <=== Set PAL and remembering settings in CRTC Cursor address register.

In CRTC3,4 its not work?

[Longshot]

"Note that bit 14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0, 1,
2. It can be at 0 or 1 on CRTCs 3 and 4. For compatibility reasons, it is strongly advised to always
set bit 14 to 1 to select PAL."

I recently discovered a trick
LD BC,#BC0F
OUT (C),C
LD A,#C7
LD BC,#3DFF
OUT (C),A.  <=== Set PAL and remembering settings in CRTC Cursor address register.

In CRTC3,4 its not work?

Not compatible.
In Basic on CRTC 3, 4...
OUT &7F00,&C7
POKE &4000,&C7
OUT &7F00,&C0
POKE &4000,&C0
OUT &BC00,&F
OUT &3DFF,&C7
PRINT HEX$(PEEK(&4000))