Z80 16-bit increment/decrement

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Ken Sheriff has another interesting blog post: Ken Shirriff's blog: The Z-80's 16-bit increment/decrement circuit reverse

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BTW, if you remember, in 32-character-width screen mode I made the comment:

Another example: ADD HL,DE
You've got a single byte instruction. 1us.
The ALU calculates E+L. 1us
The ALU calculates D+H+carry. 1us (actually, I don't know why this isn't pipelined!)
Total: 3us

Well, the reason is explained in this blog post... 

One timing consequence of using the incrementer latch for 16-bit register-to-register transfers is that it cannot be overlapped with the instruction fetch. Many Z-80 instructions are pipelined and don't finish until several cycles into the next instruction, since register and ALU operations can take place while the Z-80 is fetching the next instruction from memory. However, the PC uses the incrementer during instruction fetch to advance to the next instruction. Thus, any transfer using the incrementer latch must finish before the next instruction starts.

Also:

Unlike the ALU, the incrementer/decrementer doesn't compute parity, negative, carry, or zero values. This is why the 16-bit increment/decrement instructions don't update the status flags.