asic dma register +3

[arnoldemu]

I have been testing the plus dma and I've found a couple of strange things. I wonder if anyone has seen these before?

dcsr bit 3: this is sometimes 0 and sometimes 1. Not sure if it's floating or if it's related to something. possibly reflects "cpc" type ints, e.g. every 52 lines it is 1. No idea yet.

for the dma registers:

6c00 is channel 0 address, lsb
6c01 is channel 0 address, msb
6c02 is channel 0 pause prescale
6c03 is "unused".

It appears 6c03 is not unused, it seems to be some kind of enable/disable. I was testing it to see if it was a mirror of prescale, but no, it seems different.

When setting some bits in here prescale is ignored! So perhaps it is some kind of debugging register for dma.

The more I look the more things I find.

[Ast]

Dcsr bit 3 is an unused bit in Amstrad plus' doc. Don't know what it does or not. If someone know about it....

[Ast]

do you noticed the same trick at &6C07 or/and &6c0B ?

[arnoldemu]

do you noticed the same trick at &6C07 or/and &6c0B ?

6c07 and 6c03 seem to be the same. writing to &6c0b caused dma channel 2 to hang in my test.
I tried all possible 256 values but I didn't see a pattern and I didn't see the result I saw earlier which was prescale or pause was disabled.

if I write ff to 6c03,6c07 and 6c0b then my tests fail, dma interrupt bits are wrong, if I don't write anything then all my tests pass.

Something strange here. I did not discover their function

[Ast]

Really Strange. Does Asic still keep his secrets ?

[andycadley]

Interesting. I must have another play inside the ASIC some time.

[dragon]

Maybe  can affect another registers in another actors in the dma process. Ay ppi... or can changue a limitation in dma procces as 4096 max instructions.

Or maybe he can active the 3xxxh reversed command that is marked do not use in dma instructions table.

Only to aport a crazy diferent poin of view . The effect cannot be necesary obvius.

[arnoldemu]

Or maybe he can active the 3xxxh reversed command that is marked do not use in dma instructions table.

I already tested 3xxxh.

It is marked "unused" because 1xxx, 2xxx and 4xxx are not checked by exact number but by bit. bit 4,5,6,7 of the byte.

1xxx + 2xxx -> 3xxx is pause + repeat.

I think 6c03 etc will be test registers used to check ASIC is working correctly. The ASIC CRTC has status registers which reveal the internal comparisons of the asic crtc registers.

[PulkoMandy]

DSCR bit 3 would logically be the status of the raster interrupt.


What do you read in the unused registers? I wouldn't be surprised to find the loop position of the DMA lists there, for example.

[Ast]

Why not ? But i'm not sure....
[attachimg=1]

[arnoldemu]

DSCR bit 3 would logically be the status of the raster interrupt.

I thought this too. So I setup a test to look at when it was active to see any patterns. I have standard CPC interrupts enabled, and I don't see any patterns that would match that. In one test, bit 3 was 1, then 0 for 5 lines, then 1 again, but the pattern was not consistent.

I also tried writing bit patterns to bits 3..0 of dcsr and reading them back, this was when I saw the first problem, it was not always 0.

I will try again using pri interrupts.

What do you read in the unused registers? I wouldn't be surprised to find the loop position of the DMA lists there, for example.

I can't confirm this.

All memory between 6c00-6c0f reads the dcsr register. I can confirm this. All read the same, the value is mirrored through this range. dma address and prescale are write only. So any tests I do are write only and must then show a response I can measure (e.g. dma interrupt, dma enable, dma prescale etc).

I tried:
- testing if dcsr was mirrored here
- writing all 256 values and seeing if dma stop generating ints or pause was not effective.

My initial code pointed towards interrupts and pause being ineffective, so that the byte had bits for enables. But a second test didn't show this.

I will test again and find it.

[arnoldemu]

Why not ? But i'm not sure....
[attachimg=1]

that diagram is wrong.

dcsr:

bit 7: raster interrupt occured (PRI or "CPC interrupt")
bit 6: DMA channel *0* IRQ
bit 5: DMA channel *1* IRQ
bit 4: DMA channel *2* IRQ
bit 3: unknown
bit 2: DMA channel *2* Enable
bit 1: DMA channel *1* Enable
bit 0: DMA channel *0* Enable

[Ast]

You're righ. It's written like that in Arnold's 1.5 doc. :-)
Bit 6,5 and 4 are false in my quasar doc.

[arnoldemu]

Message removed. It was a bug in my test

[arnoldemu]

Message removed. It was a bug in my test

[arnoldemu]

Removed. I think it was a bug in my test

[Ast]

Too many bugs tonight!!!

[Ast]

Something new ?