If makes a difference when reading several sectors (using the Read Sector instruction with first sector = x, and last sector = x+1). In which case, strangely enough, the FDC will wait as long as it takes to read the given Gap after reading each sector.
So if you set a Gap to 255 when reading two sectors (no matter what the physical Gap really is), the FDC will skip the second because it will miss its beginning, and it will have to wait for another turn to read the sector. I still don't know why such behaviour exists 
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Targhan/Arkos.
Yes this makes a lot of sense. I will add extra tests for this.
The Intel 8272 document is the only one that gives a reason for GPL in read/write because it says this is to avoid a "splice point".
I've not tried it yet, but I am assuming that writing sectors or multiple sectors on this fdc, will cause gap bytes to be written after the crc for the sector, and the possibility then exists here that there will be a lost sync bit at some point when the writing stops, and so to avoid this when reading you set the read GPL to skip the problem and to ensure it writes/reads the next sector ok.
I already tried changing it with write, but only for writing a single sector and it did not corrupt the id field of the next sector so I assumed it was doing nothing here.
I can check if this happens with a special track setup
