interruptions: is there any way to change them?

[Fran123]

Hello,


I would like to use other interruption lines, for example, instead lines #1,52,104,156,208,260 using 11,62,114,166,218 and 270.

Is there any way to do it?

Thank you.

[pelrun]

On the regular CPC with no expansions, no, it's fixed in hardware.

If you're prepared to require extra hardware, then you have some more options - for instance the CTC on the PlayCity can be configured to raise an interrupt on any line.

Otherwise you're restricted to the same method demos use - catch the interrupt on an earlier line and then count cycles until you get to the desired point (or change your design to work with the interrupts you have.)

[gurneyh]

hi,

This is possible by waiting 10 lines, and reset the interrupt divider to 0.

Code Select Expand

LD BC, #7F9D
OUT (C),C
http://quasar.cpcscene.net/doku.php?id=assem:gate_array

Code Select Expand

macro WAIT_LINE n
ld b, n
@w: ds 60
djnz @w
endm

macro SET_BORDER color
ld bc, &7F10
out (c), c
ld a, color
out (c), a
endm

org &4000

di
ld hl, &c9fb
ld (&38), hl
ei

main
ld b, &f5
wloop in a, (c)
rra
jr nc, wloop

SET_BORDER &54
WAIT_LINE 10

ld bc, &7F9d
out (c), c


halt
SET_BORDER &44

halt
SET_BORDER &55

halt
SET_BORDER &5c

halt
SET_BORDER &58

halt
SET_BORDER &5D

jp main
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[Nworc]

Guys, I haven't checked the following, it's just an idea ...but you know, that:

In the CPC the Gate Array generates maskable interrupts, to do this it uses the HSYNC and VSYNC signals from the CRTC, a 6-bit internal counter and monitors the interrupt acknowledge from the Z80.

The 6-bit counter is incremented after each HSYNC from the CRTC. (When standard CRTC display settings are used, this is equivalent to counting scan-lines).

So, the regular interrupt timing is: a new interrupt every 52 scanlines, which is 52 * 64 NOPs (or microseconds). However, if you tweak the time between two HSYNC signals, you could get more interrupts in the same time interval. Say, if you set Reg 0 of the CRTC to 31, you would get a new interrupt every 52 * 32 NOPs. Don't you think?

Now, let's just ignore all the restrictions we have or might have when reprogramming the CRTC (e.g. you have you check when it accepts new data, you have to make sure that even if you tweak around, a nice HSYNC comes every 64 microseconds not to confuse the monitor, a nice VSYNC should come every 64 * 52 * 6 microseconds), so if we just ignore all that, you could try the following:

If you set Reg 0 to 31 for let's say 10 scanlines (so that each scanline now takes half the time: 32 microseconds), you would shift the first (or second) interrupt of the screen 5 scanlines of length 64 microseconds to the top. Of cause you would have to compensate for this at the end of the screen to program 5 scanlines to be of 128 microseconds length, so that the total time of a full frame stays the same.

I currently have no time to test this, but if you do, please tell us the result.

Hardware wise the circuit of a CRT monitor should tolerate if a HSYNC is missed out (e.g. in the case of the size of 128 microseconds) as the cicuit would just create one after a short delay. I just don't know what happens if you happen to have two of them in a 64 microsecond time interval, this should be checked. By physics the oscillator would not be ready to get triggered that early, so that the too early HSYNC is just ignored, but that should be checked - there's a little risk to blow you monitor, so be warned.

[andycadley]

The method by gurneyh of resetting the interrupt divider is probably the way to go. It does still involve some waiting every frame which isn't ideal but it is probably easier to have a fixed block of code at the start of the frame that can actually do useful work as long as you're careful about timing.

Or use the Plus machines and set the PRI to fire wherever you want, of course. 

[Nworc]

Very nice, I didn't knew that resetting trick. Thanks.

[abalore]

The method by gurneyh of resetting the interrupt divider is probably the way to go. It does still involve some waiting every frame which isn't ideal but it is probably easier to have a fixed block of code at the start of the frame that can actually do useful work as long as you're careful about timing.

Or use the Plus machines and set the PRI to fire wherever you want, of course. 

Just to point out you don't need to waste the waiting time, you can run a fixed duration routine like a music player or similar, and fill the remaining cycles with NOP

[gurneyh]

Guys, I haven't checked the following, it's just an idea ...but you know, that:

In the CPC the Gate Array generates maskable interrupts, to do this it uses the HSYNC and VSYNC signals from the CRTC, a 6-bit internal counter and monitors the interrupt acknowledge from the Z80.
The 6-bit counter is incremented after each HSYNC from the CRTC. (When standard CRTC display settings are used, this is equivalent to counting scan-lines).

So, the regular interrupt timing is: a new interrupt every 52 scanlines, which is 52 * 64 NOPs (or microseconds). However, if you tweak the time between two HSYNC signals, you could get more interrupts in the same time interval. Say, if you set Reg 0 of the CRTC to 31, you would get a new interrupt every 52 * 32 NOPs. Don't you think?
Now, let's just ignore all the restrictions we have or might have when reprogramming the CRTC (e.g. you have you check when it accepts new data, you have to make sure that even if you tweak around, a nice HSYNC comes every 64 microseconds not to confuse the monitor, a nice VSYNC should come every 64 * 52 * 6 microseconds), so if we just ignore all that, you could try the following:
If you set Reg 0 to 31 for let's say 10 scanlines (so that each scanline now takes half the time: 32 microseconds), you would shift the first (or second) interrupt of the screen 5 scanlines of length 64 microseconds to the top. Of cause you would have to compensate for this at the end of the screen to program 5 scanlines to be of 128 microseconds length, so that the total time of a full frame stays the same.
I currently have no time to test this, but if you do, please tell us the result.
Hardware wise the circuit of a CRT monitor should tolerate if a HSYNC is missed out (e.g. in the case of the size of 128 microseconds) as the cicuit would just create one after a short delay. I just don't know what happens if you happen to have two of them in a 64 microsecond time interval, this should be checked. By physics the oscillator would not be ready to get triggered that early, so that the too early HSYNC is just ignored, but that should be checked - there's a little risk to blow you monitor, so be warned.

That sounds pretty technical, well I don't think I can implement it.
But if I understand the theory, it seems viable

[McArti0]

10 FRAME : OUT &7F00,&95 : GOTO 10

It's WORK !!!