Besides if they're using R9=0 the game won't run on CRTC type 2.
There's no interest to modify the address of each scanline if you want to avoid "inc hl".
You just need to modify the character address. So you don't need in this case to set R9=0.
BTW what's your opinion about the game engine???
The images I saw on the promotional video indicate that there has already been a lot of work.
I think there are dynamic splitscreens that show the exploitation of the crtc.
The engine is fast and I think the stack is hugely solicited for the displays.
I think it is always a good thing when the resources are well exploited.
I expect to see the playability of the finished game, with the other vehicles and the sound effects.
I hope this project will go to the end because finishing a game is also a big workload.
There's a technique called RVI that will allow it to run on CRTC type 2. I've been trying to find information on it. I found a French forum that explains a bit about it - but using Google Translate is not ideal
RVI is a French acronym for "Rupture Verticale Invisible" (Vertical Invisible Rupture)
This technique was imagined and applied by Overflow in its "S&KOH" demo in 1991.
It consists of creating small screens in the "invisible part of screen" to change several times of block, in order to choose the block displayed on the following line.
One method consist to change R0 and R9 to do it. Small screens can last 2 nop (for example R0=1 for 14 nop (in the "invisible" area of screen), and R0 = 49 for 50 nop in the visible area).
This creates an interdependency between the lines to be managed. But you can imagine others funny methods to succeed.
Of course you can also make visible splits in the middle of the screen. (However, on some crtc, a small border area appears between each screen)
I presume losing the HBL at the line end causes a sync to happen which in turn makes the split happen.
You make a confusion between synchronization and construction of the image.
The CRTC has several registers and counters to build the image.
In general, when these counters return to 0, the transition causes the management of other counters and registers of the circuit.
In particular, taking into account the memory address present in R12.R13 of the crtc (the "split")
Preferably, each line must be 64 nop and the screen consists of 312 lines.
The CRTC must, however, generate an image that conforms to the standards of the monitor.
To synchronize this image, the monitor relies on signals generated by the CRTC.
For the vertical position it is R7-CRTC for the character line or the VBL must occur.
For the horizontal position it is R2-CRTC for the position of the character where the HBL occurs
(and R3-CRTC for its size (this can be used to shift the scren with 1 byte instead of 2)).
It is not advised to move these sync areas from one line to another.
Except if you want to obtain an analogical deformation of the image (this has been used by many demos)
If you generate several HBLs on one line, the monitor may have trouble knowing which hbl to use to stabilize the image horizontally.
However, by reducing the size of the "visible" HBL, you can easily generate several hbl on one line.
This is useful, for example, if you want to change the graphics mode multiple times per line (then hbl size must be 2 nop, which is the min delay for the gate array to succeed).
PRI is an acronym used on Amstrad Plus to define the register that defines the precise line on which a raster interrupt should occur.
In general, the interest is to reprogram an interruption from the previous one.
On CPC OLD interrupts occur on the basis of 2 counters, and every 52 hbl (C32 + C20).
When an interruption occurs, the counter are not affected.
But when the 2 counters have finished their count, an interruption becomes pending.
In general, with 1 hbl per line, you have to wait 52 lines for an interrupt to occur.
If you want an interruption to occur "earlier", you need to generate several hbls on the line or allow a first pending interrupt on hold manually (ei).
In the latter case, it is necessary to pay attention where the pending interrupt is acknowledged.
Because if it occurs while C20 is counting, then the acknowledgment for C32 is cleared, which results in a shift of 32 lines.
So to define an interruption that occurs before 52 hbl, you have to sacrifice time and display.
Conversely, you can delay the moment when an interruption occurs (thus more than 52 hbl) by resetting the counter (via the gate array).
You can also simply acknowledge or allow interruptions where you want.
Topic: Vespertino - How's this being done? (speculation!) (Read 2267 times)